This can be nullptr and ubsan found a couple of cases in LLVM's unit
tests.

This patch adds our first integration test for scalable vectorisation in
Linalg. It simply runs `linalg.fill` to fill a scalable vector with a
pre-defined f32 value. The result is printed to stdout.

Note that with scalable architectures, the vector size is not know at
compile time, but it is known at runtime. For this reason, the length of
the output generated by the new test depends on the hardware implementation. For
Arm's SVE we do know that there will be at least 4 f32 elements in every
scalable vector register. CHECK lines were designed accordingly.

In order to see what happens for different implementations of SVE, you
can use the following QEMU settings:
  * qemu-aarch64 -cpu max,sve128=on
  * qemu-aarch64 -cpu max,sve512=on

ATM, this test is only enabled when `MLIR_RUN_ARM_SVE_TESTS` is set.

Differential Revision: https://reviews.llvm.org/D155839

Ignore the expressions and re-do the tests without all the "result
ignored" expected warnings. Those are expected, given the nature of the
tests.

Differential Revision: https://reviews.llvm.org/D149831

The inner 1d vector row can be summed with vector.reduction op. The
earlier mul reduction can't be updated similarly as it currently crashes
in the backend with:

  LLVM ERROR: Expanding reductions for scalable vectors is undefined.

Reviewed By: awarzynski, dcaballe

Differential Revision: https://reviews.llvm.org/D156701

Currently a loop is materialized when lowering ArmSME loads and stores
to intrinsics. This patch introduces two new ops to the ArmSME dialect
that map 1-1 with intrinsics:

  1. arm_sme.load_tile_slice  - Loads a 1D tile slice from
     memory into a 2D SME "virtual tile".
  2. arm_sme.store_tile_slice - Stores a 1D tile slice from a 2D SME
     "virtual tile" into memory.

As well as a new conversion pass '-convert-arm-sme-to-scf' that
materializes loops with these ops. The existing load/store lowering to
intrinsics is updated to use these ops.

Depends on D156517

Discourse thread:
https://discourse.llvm.org/t/loop-materialization-in-armsme/72354

Reviewed By: awarzynski, dcaballe, WanderAway

Differential Revision: https://reviews.llvm.org/D156467

In degenerate cases, it is possible for unreachable code removal
to remove the current instruction. However, we still return the
instruction to report a change, resulting in a use after free.

Instead, perform the change reporting in the same way as
eraseInstFromFunction() does, by directly setting MadeIRChange
and returning nullptr.

Fixes https://github.com/llvm/llvm-project/issues/64235.

The Base expression might cause side-effects, so we still have to
evaluate it.

Differential Revision: https://reviews.llvm.org/D149828

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D156597

The 'get_tile_id' op is currently marked as pure so CSE thinks these ops
are equivalent and replaces with them a single one. This patch removes
pure to prevent this.

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D156558

Add -canonicalize to simplify Vector to ArmSME test and use CHECK-DAG.

Reviewed By: awarzynski, dcaballe

Differential Revision: https://reviews.llvm.org/D156517

Create a mix-in class with an overloaded constructor that makes the
return type optional.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D156561

Currently, we consider any instruction that might read from memory to be unsafe for phi-of-ops.
This patch refines that by walking the clobbering memDefs until we either hit a block that
strictly dominates the phi block (safe) or we hit a clobbering memPhi (unsafe).

Differential Revision: https://reviews.llvm.org/D156055

Differential Revision: https://reviews.llvm.org/D154475

The last use was removed by:

  commit 6b31e63b
  Author: Kazu Hirata <kazu@google.com>
  Date:   Sat Jun 24 07:33:50 2023 -0700

It's valuable to have document highlights for labels and be able to find
references to them.

Reviewed By: nridge

Differential Revision: https://reviews.llvm.org/D150124

This reverts commit 3e386b22.

Next to the original fold, this also implements an unnecessary and
inappropriate simplifyICmpWithDominatingAssume() based fold.

This adds support for reprocessing new instructions that were generated
by the target's eliminateFrameIndex.

Backwards frame index elimination uses backwards register scavenging,
which is preferred because it does not rely on accurate kill flags.

Differential Revision: https://reviews.llvm.org/D156690

This adds notes for the change from https://reviews.llvm.org/D146398 /
fcbbd964.

Differential Revision: https://reviews.llvm.org/D156627

Differential Revision: https://reviews.llvm.org/D154038

The RISC-V psABI recently added __bf16 in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367.
Now we can enable this new type in clang.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150929

The refactored template can now be used with MachineVerifier.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D156522

Previously when llvm.reduce.* lowered, riscv backend created scalar vector with
netural element as start value. For llvm.reduce.and/or/min/max/fmax/fmin, we
could use the first element of source as the start value. It's benefit for RVV
since we could just use source vector as start vector.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155929

We check the loop trip count is known a power of 2 to determine
whether the tail loop can be eliminated in D146199.
However, the remainder loop of mask scalable loop can also be removed
If we know the mask is always going to be true for every vector iteration.
Depend on the assume of power-of-two vscale on D155350

proofs： https://alive2.llvm.org/ce/z/FkTMoy

Fix https://github.com/llvm/llvm-project/issues/63616.

Reviewed By: goldstein.w.n, nikic, david-arm, paulwalker-arm
Differential Revision: https://reviews.llvm.org/D154953

Differential Revision: https://reviews.llvm.org/D156591

Currentlt, bf16 operations are automatically supported by promoting to float. This patch adds bf16 support by ensuring that load extension / truncate store operations are properly expanded.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D156646

Reviewed By: #libc, ldionne

Spies: wangpc, libcxx-commits

Differential Revision: https://reviews.llvm.org/D155512

This reverts commit 77ef88d7. There is
an unimaged crash report after landing this. See
https://reviews.llvm.org/D154695.

Reviewed By: #libc, Mordante

Spies: Mordante, libcxx-commits

Differential Revision: https://reviews.llvm.org/D155325

Limiting the test to only X86.

Reviewed By: Amir

Differential Revision: https://reviews.llvm.org/D156765

Reviewed By: #libc, Mordante

Spies: arichardson, Mordante, libcxx-commits

Differential Revision: https://reviews.llvm.org/D155260

Reviewed By: #libc, Mordante

Spies: Mordante, libcxx-commits

Differential Revision: https://reviews.llvm.org/D155259

Reviewed By: #libc, Mordante

Spies: Mordante, arichardson, libcxx-commits

Differential Revision: https://reviews.llvm.org/D155258

This reverts commit a496c8be.

The workaround in c26dfc81 should work
around the underlying problem with SUBREG_TO_REG.

Handle both v0 and v1 operands that may be converted to SPIR-V scalars.

Fixes: https://github.com/llvm/llvm-project/issues/64271

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D156717