Details: https://github.com/llvm/llvm-project/issues/61022

This reverts commit b5bf6f63.

Represent scalable type sizes using C * vscale, where vscale is
the vscale constant expression. This exposes a bit more information
to SCEV, because the vscale multiplier is explicitly modeled in SCEV
(rather than part of the sizeof expression).

This is mainly intended as an alternative to D143642.

Differential Revision: https://reviews.llvm.org/D144624

Differential Revision: https://reviews.llvm.org/D143560

llvm-debuginfo-analyzer is a command line tool that processes debug
info contained in a binary file and produces a debug information
format agnostic “Logical View”, which is a high-level semantic
representation of the debug info, independent of the low-level
format.

The code has been divided into the following patches:

1) Interval tree
2) Driver and documentation
3) Logical elements
4) Locations and ranges
5) Select elements
6) Warning and internal options
7) Compare elements
8) ELF Reader
9) CodeView Reader

Full details:
https://discourse.llvm.org/t/llvm-dev-rfc-llvm-dva-debug-information-visual-analyzer/62570

This patch:

This is a high level summary of the changes in this patch.

CodeView Reader
- Support for CodeView/PDB.
  LVCodeViewReader, LVTypeVisitor, LVSymbolVisitor, LVLogicalVisitor

Reviewed By: psamolysov, probinson, djtodoro, zequanwu

Differential Revision: https://reviews.llvm.org/D125784

incompatible flags in the CLI tool.

Process cases when phi incoming in predecessor block has select
instruction, and this select address is unavailable, but there
are addresses translated from both sides of select instruction.

Differential Revision: https://reviews.llvm.org/D142705

This commit ensures that no empty debug metadata strings are exported as
these are not legal names. Additionally, this commit ensures that
non-existing strings are not accidentially imported as empty strings.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144263

Update a few tests where the checks aren't exactly kosher.

Differential Revision: https://reviews.llvm.org/D144639

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D144267

Incorrect API usage was detected by D144552.

Differential Revision: https://reviews.llvm.org/D144636

- always use genExprAddr when lowering to HLFIR: it does not create
  temporary for array sections without vector subscripts, so there is
  no need to have custom logic.

- update mangling to deal with AssocDetailsEntity. Their name is
  required in HLFIR so that it can be added to the hlfir.declare
  that is created for the selector once it is lowered. This should
  allow getting debug info for selector when debug info are generated
  from hlfir.declare.

The rest of associate construct lowering is unchanged and shared with
the current lowering.

This patch also enables select type lowering to work properly, but some
other todos (mainly about parent component references) prevents porting
the tests for now, so this will be done later.

Differential Revision: https://reviews.llvm.org/D144740

Nothing much to do except set the right attributes on hlfir.assign.

Differential Revision: https://reviews.llvm.org/D144727

Differential Revision: https://reviews.llvm.org/D144723

Inserting scalar result of 'uaddlv' neon intrinsic function to a destination vector currently makes use of the integer unit. Subsequent patches will eliminate the redundant use of the integer registers in a more generic way that will include this special case. This is an initial set of tests for this functionality.

Differential Revision: https://reviews.llvm.org/D143038

We use `use64bitIndex` in the option to decide the target device
address bitwidth. This makes it consistent with index type
conversion too.

Reviewed By: kuhar

Differential Revision: https://reviews.llvm.org/D144827

Vulkan requires GPU processor ID/count builtin variables to be
32-bit scalar or vector for all the cases. Similarly there
are special requirements for OpenCL. We need to make sure those
rules are respected when converting using 64bit for index.

Reviewed By: kuhar

Differential Revision: https://reviews.llvm.org/D144819

The asm printer grew the ability to automatically fall back to the
generic format for invalid ops, so this logic doesn't need to be in the
bindings anymore. The printer already handles supressing diagnostics
that get emitted while checking if the op is valid.

Reviewed By: mehdi_amini, stellaraccident

Differential Revision: https://reviews.llvm.org/D144805

Signed-off-by: Jun Zhang <jun@junz.org>

If a template function contained a pragma that made it strictfp, code
generation for such function crashed, because the instantiation did not
have strictfp attribute. As a solution this attribute is copied from the
template to instantiation.

Differential Revision: https://reviews.llvm.org/D143919

/data/llvm-project/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp:1200:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
  case X86II::RawFrm:
  ^

1. Add a variable `HasRegOp` to record if the instruction has a register operand
2. Enumerate all the formats with a register operand in the switch
2. Add a default (unreachable) label in the switch (suggested by @reames)

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D144776

We use this combine in the AArch64 postlegalizer combiner, which causes this
function to query the legalizer rules for the action for an invalid opcode/type
combination (G_AND and p0). Moving the legalizer query until after the validity
check in matchHoistLogicOpWithSameOpcodeHands() fixes this.

This patch implements the exception handling rules found in
N4849 14.4 and as a result fixes many false positives in
the bugprone-exception-escape checker.

Differential Revision: https://reviews.llvm.org/D135495

This commit just adds options to control index type bitwidth in
GPUToSPIRV conversion, and updates tests to prepare for 64bit
index conversion.

Reviewed By: kuhar

Differential Revision: https://reviews.llvm.org/D144826

The `tyname_cell` definitions at the top are now all the same, so
replace them with a single `alloca_cell` type.

Preparation for further additions.

This patch adds support of DWARFv5 .debug_rnglists table.
As DWARFLinker resolves relocations, it is able to always
use DW_FORM_addr instead of DW_FORM_addrx. DW_FORM_addrx
helps to minimize number of relocations, it is also used for
split DWARF. Both of these cases are not relevant for the
DWARFLinker. Thus, this patch converts all DW_FORM_addrx
forms into the DW_FORM_addr. And, as the result, it converts
range lists of DW_FORM_rnglistx form into the DW_FORM_sec_offset.
For the --update case all DW_FORM_addrx, DW_FORM_rnglistx
are preserved as is.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D143903

Added: OR, SMAX, SMIN, UMAX, UMIN, ABS, SHL, SRL, SRA, MUL

Intentionally not generically using TLI.isBinOp as that causes
regressions as there are many binops that cannot combine with masked
instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143860

Differential Revision: https://reviews.llvm.org/D144144

`{v}blend{d|ps|pd}` is preferable to `{v}blendw` so widen so that we
can match it.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143789

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143788

Invariant.group's are not sufficiently handled by LICM. Specifically,
if a given invariant.group loaded pointer is not overwritten between
the start of a loop, and its use in the load, it can be hoisted.
The invariant.group (on an already invariant pointer operand) ensures
the result is the same. If it is not overwritten between the start
of the loop and the load, it is therefore legal to hoist.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D144053

Fix https://github.com/llvm/llvm-project/issues/59740.
NOTE: retry as we can't reproduce the break locally when first commit.

Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D141188