- Oct 14, 2021
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Biju Das authored
Enable Ethernet{0,1} interfaces on RZ/G2L SMARC EVK. Signed-off-by:Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211013075647.32231-3-biju.das.jz@bp.renesas.com Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: -
Niklas Söderlund authored
The different port@ entries of the adv7482 nodes shall be encapsulated in a ports node, add one. This change does not change how the driver parses the DT and no driver change is needed. The change however makes it possible to validate the source files with a correct json-schema. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20211012183431.718691-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by:
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Niklas Söderlund authored
The V3U have 32 VIN, 4 CSI-2 and 4 ISP nodes that interact with each other for video capture. Add all nodes and record how they are interconnected. Signed-off-by:
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- Oct 11, 2021
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Biju Das authored
This patch enables microSD card slot connected to SDHI1 on RZ/G2L SMARC platform. Signed-off-by:
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Biju Das authored
RZ/G2L SoM has both 64 GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2] switch position. This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch setting logic for device selection between eMMC and microSD slot connected to SDHI0. Set SW1[2] to position 2/OFF for selecting eMMC Set SW1[2] to position 3/ON for selecting microSD This patch enables eMMC on RZ/G2L SMARC platform by default. Signed-off-by:
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- Oct 08, 2021
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Biju Das authored
Add SDHI{0, 1} nodes to RZ/G2L SoC DTSI. Signed-off-by: -
Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211006085836.42155-5-wsa+renesas@sang-engineering.com Signed-off-by:
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Duc Nguyen authored
Add device node for RPC on R8A779A0 SoC. Signed-off-by:
Duc Nguyen <duc.nguyen.ub@renesas.com> [wsa: rebased] Signed-off-by:
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Lad Prabhakar authored
Add SPI Multi I/O Bus controller node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
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- Sep 28, 2021
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Geert Uytterhoeven authored
Describe all Ethernet PHY reset GPIOs on R-Car Gen3 boards, to avoid relying solely on boot loaders to bring PHYs out of reset. Signed-off-by:
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Geert Uytterhoeven authored
Describe all Ethernet PHY reset GPIOs on RZ/G1 boards, to avoid relying solely on boot loaders to bring PHYs out of reset. Signed-off-by:
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Geert Uytterhoeven authored
Describe all Ethernet PHY reset GPIOs on R-Mobile boards, to avoid relying solely on boot loaders to bring PHYs out of reset. Signed-off-by:
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Realtek RTL8211E PHYs on RZ/G2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/3b366e3dddd4d3cd7e89b92d3a8f78f6dc18e244.1631174218.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ9031 PHYs on R-Car Gen3 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Atheros AR8031 PHYs on RZ/G2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/3f1b58756f149f0c634c66abaecc88e699f4c3cc.1631174218.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Renesas uPD60610 or uPD60611 PHYs on RZ/A1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Realtek RTL8201FL PHYs on RZ/A2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing SMSC LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ9031 PHYs on RZ/G1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ8081 PHYs on RZ/G1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
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Geert Uytterhoeven authored
Add compatible values to Ethernet PHY subnodes representing Micrel KSZ8041 PHYs on RZ/G1 and R-Car Gen2 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by:
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Geert Uytterhoeven authored
While networking works fine in RGMII mode when using the Linux generic PHY driver, it fails when using the Atheros PHY driver. Fix this by correcting the Ethernet PHY mode to RGMII-RXID, which works fine with both drivers. Fixes: a5200e63 ("arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling") Reported-by:
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Geert Uytterhoeven authored
According to schematics, and confirmed by ID_REV register contents, the Ethernet controllers on various development board are not SMSC LAN9220, but different variants: - KZM-A9-Dual and KZM-A9-GT: LAN9221, - Bock-W and Marzen: LAN89218AQ. Update the compatible values accordingly. Signed-off-by:
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- Sep 24, 2021
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Lad Prabhakar authored
Enable CANFD on RZ/G2L SMARC platform. Signed-off-by:
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Lad Prabhakar authored
Enable the ADC which is present on RZ/G2L SMARC SOM. Signed-off-by:
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Lad Prabhakar authored
Move extal and memory nodes to SOM DTSI. Signed-off-by:
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Kieran Bingham authored
Add support for SW47, SW48 and SW49 via "gpio-keys" on the R-Car V3U Falcon board. Signed-off-by:
Kieran Bingham <kieran.bingham@ideasonboard.com> Link: https://lore.kernel.org/r/20210922201314.3205674-1-kieran.bingham@ideasonboard.com Signed-off-by:
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Biju Das authored
Add audio routing for Mic with bias to reduce noise when doing audio capture. Signed-off-by:
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Biju Das authored
Enable audio on RZ/G2L SMARC EVK by linking SSI0 with WM8978 audio CODEC. Signed-off-by:
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Biju Das authored
Add WM8978 sound codec node to RZ/G2L SMARC EVK. Signed-off-by:
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Biju Das authored
Add dmac phandles to SSI nodes to support DMA operation. Signed-off-by:
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Biju Das authored
Enable I2C{0,1,3} support on RZ/G2L SMARC EVK. Signed-off-by: -
Biju Das authored
Enable USB2.0 Host/Device support on RZ/G2L SMARC EVK. Signed-off-by:
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- Sep 20, 2021
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Yoshihiro Shimoda authored
Add iommus into sdhi node. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210901111305.570206-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by:
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Yoshihiro Shimoda authored
Add IPMMU nodes for r8a779a0. Note that this patch sets the power domain of IPMMU-VC0 is Always-On tentatively because the SoC doesn't have A3VC power domain. Signed-off-by:
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Duc Nguyen authored
This patch adds TPU node for R-Car V3U (r8a779a0) SoC. Signed-off-by:
LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by:
Wolfram Sang <wsa@kernel.org> Link: https://lore.kernel.org/r/20210901091725.35610-3-wsa+renesas@sang-engineering.com Signed-off-by:
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Wolfram Sang authored
Add the missing TPU node for the R-Car M3-W+ SoC. Signed-off-by:
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Biju Das authored
Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI. Signed-off-by: -
Biju Das authored
Add external audio clocks nodes to RZ/G2L (a.k.a R9A07G044) SoC DTSI. The external audio clocks are configured as 0 Hz fixed frequency clocks by default. Boards that provide audio clocks should override them. Signed-off-by:
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