Commit eb675043 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a779a0: Add IPMMU nodes 



Add IPMMU nodes for r8a779a0. Note that this patch sets the power
domain of IPMMU-VC0 is Always-On tentatively because the SoC doesn't
have A3VC power domain.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210901111305.570206-2-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent bdd8b005

arch/arm64/boot/dts/renesas/r8a779a0.dtsi

+97 −0
Original line number Diff line number Diff line
@@ -1104,6 +1104,103 @@ mmc0: mmc@ee140000 { 
			status = "disabled";

		};



		ipmmu_rt0: iommu@ee480000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xee480000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 10>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_rt1: iommu@ee4c0000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xee4c0000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 19>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_ds0: iommu@eed00000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeed00000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 0>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_ds1: iommu@eed40000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeed40000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 1>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_ir: iommu@eed80000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeed80000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 3>;

			power-domains = <&sysc R8A779A0_PD_A3IR>;

			#iommu-cells = <1>;

		};



		ipmmu_vc0: iommu@eedc0000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeedc0000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 12>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_vi0: iommu@eee80000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeee80000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 14>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_vi1: iommu@eeec0000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeeec0000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 15>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_3dg: iommu@eee00000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeee00000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 6>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_vip0: iommu@eef00000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeef00000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 5>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_vip1: iommu@eef40000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeef40000 0 0x20000>;

			renesas,ipmmu-main = <&ipmmu_mm 11>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		ipmmu_mm: iommu@eefc0000 {

			compatible = "renesas,ipmmu-r8a779a0";

			reg = <0 0xeefc0000 0 0x20000>;

			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			#iommu-cells = <1>;

		};



		gic: interrupt-controller@f1000000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;