Commit 7ae09309 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: rzg2l-smarc: Enable CANFD 



Enable CANFD on RZ/G2L SMARC platform.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210924102338.11595-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 03f7d78e

arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

+40 −0
Original line number Diff line number Diff line
@@ -80,6 +80,20 @@ &audio_clk2{ 
	clock-frequency = <12288000>;

};



&canfd {

	pinctrl-0 = <&can0_pins &can1_pins>;

	pinctrl-names = "default";

	status = "okay";



	channel0 {

		status = "okay";

	};



	channel1 {

		status = "okay";

	};

};



&ehci0 {

	dr_mode = "otg";

	status = "okay";
@@ -139,6 +153,32 @@ &pinctrl { 
	pinctrl-0 = <&sound_clk_pins>;

	pinctrl-names = "default";



	can0_pins: can0 {

		pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */

			 <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */

	};



	/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */

	can0-stb {

		gpio-hog;

		gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;

		output-low;

		line-name = "can0_stb";

	};



	can1_pins: can1 {

		pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */

			 <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */

	};



	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */

	can1-stb {

		gpio-hog;

		gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;

		output-low;

		line-name = "can1_stb";

	};



	i2c0_pins: i2c0 {

		pins = "RIIC0_SDA", "RIIC0_SCL";

		input-enable;