* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen

* Add CLI support for GenVerilogMemBehaviorModelAnno

* Add simple test for GenVerilogMemBehaviorModelAnno

* Fix for review

1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.

* Format DumpMemoryAnnotations & ReplSeqMemTests

* Fix for review

1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog

* Fix ReadWritePort mask name

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add more inline renaming test cases

* InlineInstances: fix renaming for local targets

* run scalafmt

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

LowerTypes creates a lot of mappings for the RenameMap. The built-in
.distinct of renames becomes a performance program for designs with
deeply nested Aggregates. Because LowerTypes does not create duplicate
renames, it can safely eschew the safety of using .distinct via a
private internal API.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add os-lib to dependency.

* use os-lib in Z3ModelChecker

* fix for review by Kevin.

This function will safely wrap any unserializeable annotations in
UnserializeableAnnotations so that they can be safely serialized to JSON
for logging.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Implement MFC-style source locator compression

* Fix formatting issues

* Fix emitting empty FileInfo if the firrtl doesn't have one

* Remove '.scala' requirement in FileInfo parsing regex

* Handle parsing of FileInfos with no line/col nums

* Split FileInfos only if they match

This should fix any issues with FileInfos that do not use the "file line:col"
format, and allow any valid firrtl using these info comments to compile.

* Add unit tests for locator compression

* Move InfoTests to InfoSpec class

* Fix existing unit tests with fileinfo comments

* Add unit tests to ignore the algorithm's own output

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* remove all deprecations, switch to new API.

* Add MemLibOutConfigFileAnnotation to replace ConfWriter.

* Inline CreateMemoryAnnotations in ReplSeqMem.

* Dont use ConfWriter anymore.

* Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation.

* Fix for review.

0. Since DependencyAPI only initiate transform only once, ListBuffer is
   dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
   MemLibOutConfigFileAnnotation also extends from which now.

* Use two annotations converting and storing DefMemory.

0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation
   creating PinAnnotation.
1. add DumpMemoryAnnotations to convert from
   AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
   HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
   DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform

* Fix for review.

0. replace AnnotatedMemoriesCollectorAnnotation with immutable
   AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.

* private functions in ReplaceMemMacros transform.

* scalafmt

* remove ConfWriter API.

Looks like a typo/auto-merge hiccup.

Co-authored-by: jackkoenig <jackkoenig@users.noreply.github.com>

With Stage/Phase, users can provide complex functionality at the phase
level rather than just the transform level. It is useful to have the
same logging information at that level. Note that this change still logs
transforms in the same way, but now the time in inclusive of annotation
renaming which can also [unfortunately] be slow.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fixes #2173

Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:

    circuit Foo :
      module Foo :
        input a: UInt<3>
        output b: UInt<4>
        b <= asUInt(xor(asSInt(a), SInt<4>(0)))

This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.

This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.

Also make minor updates to CI workflow