Fix a bug where a type check would always yield true. This caused a
bug where allow/block-list annotations would be incorrectly applied to
all subtypes of ManipulateNames.

The tests are updated to check that this now works.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add testcase for empty message

* ConvertAsserts maps each assert into a gated print-and-stop
* ConvertAsserts is an optional prereq of RemoveVerificationStatements
* ConvertAsserts generates Low FIRRTL
* Drop print for asserts that have an empty message
* Fix scaladoc formatting from review

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Batch renames in LowerTypes

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add benchmarking for LowerTypes

Add infrastructure of benchmarking Transforms (in addition to
existing infra for Passes). Also run System.gc between each timed
benchmark to improve stability.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Refactor ManipulateNames to use Target

Adds an options to the FIRRTL compiler command line to schedule the
LowerCaseNames and UpperCaseNames transforms.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds three new transforms:

  - (abstract) LetterCaseTransform parent of case manipulation
  - LowerCaseNames to lower case all names
  - UpperCaseNames to upper case all names

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Add tests for the ManipulateNames transform.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Add a new annotation that stores the resulting name of an allowlist
name to be manipulated.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Rewrite of RemoveKeywordCollisions into a more generic
ManipulateNames. The new ManipulateNames transform is abstract in a
'(String, Namespace) => String' method that can be used for arbitrary
manipulation of names in a circuit. The software architecture remains
mostly the same (a rename map is used as the underlying data store).
However, the new ManipulateNames used Target as opposed to Named.

Add the ability for naming to be selectively enabled or disabled via:
  - ManipulateNamesAllowlistAnnotation
  - ManipulateNamesBlocklistAnnotation

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

If a module has ports of type Bundle that are used in aggregate
connections in parent modules, Dedup cannot change the names of the
fields of the Bundle or it would change the semantics of the connection.
Dedup now detects this case and refrains from agnostifying the ports of
such modules to prevent this issue.

* Add assume, assert, cover statements
* Assert submodule assumptions
* Add warning when removing verification statements
* Remove System Verilog behaviour emitter warning
* Add option to disable AssertSubmoduleAssumptions
* Document verification statements in the spec

The syntax for the new statements is

    assert(clk, cond, en, msg)
    assume(clk, cond, en, msg)
    cover(clk, cond, en, msg)

With assert as a representative example, the semantics is as follows:
`clk` is the clock, `cond` is the expression being asserted, `en` is the
enable signal (if `en` is low then the assert is not checked) and `msg`
is a string message intended to be reported as an error message by the
model checker if the assertion fails.

In the Verilog emitter, the new statements are handled by a new
`formals` map, which groups the statements by clock domain. All model
checking statements are then emitted within the context of an `ifdef
FORMAL` block, which allows model checking tools (like Symbiyosys) to
utilize the statements while keeping them out of synthesis flows.

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

Deprecate PreservesAll Trait, Remove Usages

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Support Memory Initialization for Simulation and FPGA Flows

This adds a minimal annotation that allows users to
influence if memories are randomly initialized,
if all entries are initialized to the same scalar or
if each entry should be initialized to a different value.
We use the init block in order to initialize memories
which is supported by verilator as well as yosys
and has previously been used to randomize the initial
memory contents.

* LowerTypes: error when trying to split up a memory with MemoryInitAnnotation

Currently the MemoryInitAnnotation only works for
ground-type memories.
We catch misuse of this annotation at the point of
the firrtl compiler at which memories on non-ground type
get split up, i.e., the LowerTypes transform.
Chisel should try to prevent annotating non-ground
type memories in the frontend, but it is nice to
have an additional check.

* MemoryInitSpec: test JSON deserialization

* MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add attributes, ifdefs to emitter.

* Make ifdef API a little cleaner.

* Remove references to ifdefs.

* Remove more of the ifdef stuff I missed

* Fix up failing tests

* Add multiple attribute test case

* Remove tpe as a parameter from Annotations.

Some general refactoring.

* Add some documentation.

* Incorporate some feedback

* Expand some spaghetti code, add comments

* Fix type signature by removing it

* bug fix in test

* Fix unchecked type parameter matches in AddDescriptionNodes.

* use target to replace name

Co-authored-by: Paul Rigge <rigge@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* delete usages of toSet for determinism

* add formatting suggestion from code review

This message informs the user, it does not indicate
a failure.

* Build ArrayBuffers in Block.mapStmt

* Have empty Block serialize as "skip"

The FIRRTL parser requires at least one indented line in each module.
Sometimes tests emit and parse modules with no contents; this ensures
there's always at least a "skip" in empty modules.

Also fix tests that expected certain skips

* Use var List as stack in Block.mapStmt impl

This replaces Iterator concatenation. In Scala 2.11, RHS recursion on
Iterators is not stack safe. This seems to have been fixed in 2.12 by
Scala PR 5033.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This provides a common Python interfaces for monitoring resource usage
of subprocesses

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Use Travis Workspaces

Add stage to build FIRRTL and share it with later steps running the
tests

* [CI] Do not sbt clean in formal_equiv.sh

This change takes advantage of shared workspace in Travis

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Use WrappedExpression instead of MemoizedHash. The benefit of memoizing
the hash pales in comparison to the cost of hashing deeply nested Types
in the AST.

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Switch to more idiomatic flatMap for Utils.expandRef

* Avoid excessively deep recursion
* Avoid overhead of DFS for shallow expression trees
* Reduce work: skip expressions that cannot contain error-containing subtrees
* Review feedback: added commentary to explain new check_widths_e structure

* Extend PassBenchmark to benchmark a particular Pass
* Add license note to file