Add ConvertAsserts transform to map asserts to Verilog-friendly nodes

* ConvertAsserts maps each assert into a gated print-and-stop
* ConvertAsserts is an optional prereq of RemoveVerificationStatements
* ConvertAsserts generates Low FIRRTL
* Drop print for asserts that have an empty message
* Fix scaladoc formatting from review

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>