Change serialize to abstract method on FirrtlNode

Fix mem infer

turned on with '--inferRW <circuit name>'

Fix use of global state in instance loop checking

Change default log level to warn

Refactor RemoveAccesses and fix bug #210.

Also increase sensitivity of thread safety checking
Fixes #159

remove ConstProp in HighFirrtlToMiddleFirrtl

Fix StringSpec generators to only choose from valid values.

Added corresponding unit test.

The old almost equivalent syntax gives the same result but can cause the
test to fail if too many invalid values are thrown away.

ConstProp before width padding causes errors for SIntLiteral

InferWidths now only fixes declaration widths

Then calls InferTypes to propagate inferred widths to expressions.
Required upgrading InferTypes to do simple width propagation.
Fixes #206  and #200.

read ports are declared outside when clauses and used multiple times, so their enables should be inserted when being replaced

Added future-release.txt

Rework Annotations

Conflicts:
	src/main/scala/firrtl/Compiler.scala
	src/main/scala/firrtl/LoweringCompilers.scala
	src/main/scala/firrtl/passes/Inline.scala
	src/test/scala/firrtlTests/AnnotationTests.scala
	src/test/scala/firrtlTests/InlineInstancesTests.scala

Fixed reg concrete syntax. #197.

Keeps track of proposed changes to add to the next version of the Firrtl spec.

Added a Chirrtl check for undeclared wires, etc.

Detects and flags cyclic module loops

Removed InferWidths after ExpandWhens

Indentation support for the ANTLR parser
    - some clean-up of the parser code (TODO: file input could be improved, more clean-up)
    - get rid of Translator and specify all syntactic rules in antlr4 grammer
    - support for else-when shorthand in the grammar
    - rename Begin to Block which makes more sense

Randomization should be controllable separately.  Verilator, for
example, already does this if it is passed --x-assign unique; doing
it redundantly reduces simulation performance.