Update Scaladoc documentation on DontTouchAnnotation to indicate that
this is an optimization barrier as opposed to just a component that
should not be DCE'd.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Relax spec on 0-bit mux select, use SFC behavior

Change the FIRRTL specification document to allow for 0-bit mux selects.
The existing ZeroWidths pass will promote these to a 1-bit, 0-valued
select signal (which effectively means that the mux can be optimized
away to just the false path).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.

* Fixes #2206

* Restore parsed MultiInfo structure in firrtl parser

* Change erroneous expected output in InfoSpec test

FileInfo compression sorts the outputted entries alphabetically, but
this test did not reflect that fact

* Fix typo in comment

* Add unit tests for file locator parsing

* Fix syntax issues and typos

* More redundant braces removed

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* smt: include firrtl statement names in SMT and btor2 output

* smt: remove println

* smt: make tests run again and fix stale ones

Apparently `private` classes aren't found by th sbt test runner.

Add a new option to the FIRRTL compiler, "--start-from = <form>".  If
used, this will cause the compiler to assume that the input FIRRTL
circuit is already in the specific form.  It will then skip unnecessary
passes given this information.

E.g., if a user requests to run "firrtl -X verilog --start-from low"
then the compiler will only run transforms necessary to get from low
FIRRTL to Verilog.  Transforms necessary for ingesting FIRRTL IR will be
run if needed (checks and type/kind/flow resolution).

To implement this, a CurrentFirrtlStateAnnotation is added.  Advanced
users can use this directly to tell the FIRRTL compiler exactly what
transforms have already been run, including the ability to ignore checks
or type/kind/flow resolution if they so desire.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add Protocol Buffer emission export

This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.

Fixes #1696.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Add Protocol Buffer emission export

* make PresetRegAnnotation public

this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
  need to be initialized at the beginning of simulation
  (e.g., for formal verification)
- to support preset registers in treadle

* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass

Add a compiler/emitter that can target minimal high form.  This will
produce output that only has CHIRRTL constructs removed.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove java.io in MustDedup

Requested by reviewer.

Remove java.io in FileUtils

Update os-lib to 0.7.8

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Update sbt-scalafix to 0.9.29

* ReplaceMemMacros: add target rename test case

* ReplaceMemMacros: rename references to instances

* fix renaming for deduped mems

* use grouped DummyAnnos to preserve order

* Apply suggestions from code review

Co-authored-by: Jack Koenig <koenig@sifive.com>

* run scalafmt

* flatten targets

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Update sbt-scalafix to 0.9.28

Update sbt-mima-plugin to 0.9.2

* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen

* Add CLI support for GenVerilogMemBehaviorModelAnno

* Add simple test for GenVerilogMemBehaviorModelAnno

* Fix for review

1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.

* Format DumpMemoryAnnotations & ReplSeqMemTests

* Fix for review

1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog

* Fix ReadWritePort mask name

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add more inline renaming test cases

* InlineInstances: fix renaming for local targets

* run scalafmt

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>