* Don't create nodes to hold Muxes with >0 void cases

* Added test case demonstrating void error

* Memoize intermediate expression when checking for WVoid-ness

(cherry picked from commit a8e8b5fc)

Fix for broken 1dcf9907 (#833) cherry-pick - bad regUpdate code.

Merge branch '1.1.x' into 1.1.5

(cherry picked from commit dcb13c96)

- Add firrtl.transforms.CombineCats
- Use CombineCats in LowFirrtlOptimization
- Modify Verilog emitter to allow for nested Cat DoPrims
- Modify firrtlEquivalenceTest to write input FIRRTL string to test directory

(cherry picked from commit b90589f5)

(cherry picked from commit 6ece732d)

With the newest version of SBT, the commandline `sbt publish-local` should be changed to `sbt publishLocal`.

(cherry picked from commit 39359141)

When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917

(cherry picked from commit 297fbda1)

- Travis unshallow if shallow clone breaks ancestry

(cherry picked from commit 1e89e416)

This makes "skip chisel tests" work properly

(cherry picked from commit 92600f1a)

This wraps interactions with a BlackBox resource file such that a
FileNotFoundException are wrapped in a BlackBoxNotFoundException and
rethrown. This provides a better, verbose error message to the user and avoids a
FileNotFoundException showing up as an internal FIRRTL error.

This adds tests that the expected exception is thrown for both
BlackBoxResourceAnno and BlackBoxResourceAnno.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 3d3bc2fb)

(cherry picked from commit 69f9060f)

* Merge makefile changes from dev/specification-fixes

- New top level makefile target: `specification`
  - Builds the specification document.

* Number all code examples.

This is more a change of convenience than anything. Referring to syntax
examples is much easier when they are numbered!

This commit is in the context of freechipsproject/firrtl#890 - Updating
examples and syntax specification is made easier if they are numbered.

- Change `verbatim` environments to `lstlisting`
- Add very basic keyword highlighting.
- Rebuild specification PDF.

 On branch dev/number-code-examples
 Changes to be committed:
	modified:   spec/spec.pdf
	modified:   spec/spec.tex

(cherry picked from commit 29e5c088)

This adds a utility, expandPrefixes, that expands a string into all
possible prefixes based on a delimiter. Any repeated occurrence of the
delimiter is viewed as a contributing to a prefix. E.g., "foo_bar" expands
to Seq("foo_", "foo_bar"). This is useful for inlining and keyword
mangling on LowForm. You would like to be able to generate a new name that
is prefix unique with respect to a namespace.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 953deb5d)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 502c8dd3)

When different levels of the circuit were annotated, the TopWiring signals of the lower levels would "run-over" the TopWiring signals of the higher levels

(cherry picked from commit ba12915e)

(cherry picked from commit 7b4bde7e)

(cherry picked from commit 860e6844)

This provides support for increased introspection of options inside of
scopt, e.g., getting an options short option (shortOpt).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 10358213)

* Filter resource file names to avoid including the same file multiple times.
Addresses issue #882.

* Use a Set instead of a Map to filter Verilog files.

* Use canonical paths for file name comparison and unify name generation.
Provide a common method for copying resources to a directory to ensure the same resource ends up with the same name if it's copied by multiple clients.

* Reduce confusion - another absolute -> canonical switch.
Use the canonical path on the verilator command line for the filter additional Verilog sources.

(cherry picked from commit 6a9710a8)

* Bump to Scala 2.12.6 and make it the default.

* Use Scala 2.11.12 for chisel tests.

* Try with Scala 2.12.4.

(cherry picked from commit 3f2e8cf6)

- Fixed edge case file name that starts with . and has no suffix

(cherry picked from commit 2c299f46)

* Support for load memory annotations in chisel
This PR
 * Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler
   * remove from VerilogCompiler
   * move to VerilogEmitter
 * Changes the verilog emitter to allow programmatic access to the verilog module declaration
   * Creating a bindable module requires headers to match
 * Provides a unit test that shows how to generate a bindable module.

* Binding support
Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading

* Binding support
- Fixed bug that handled suffixes on memory initializing files

* Binding support
- Add a bit more doc to the API provided by the VerilogRenderer

(cherry picked from commit 1dcf9907)

This reverts commit 1d4691f5.

This reverts commit 39b6a25d.

This reverts commit 44b5c853.

This reverts commit 058afbf9.

master 897dad03

# Conflicts:
#	build.sbt

 - selected changes from master for 1.1.3 release
 - bump version in build.sbt

* bug fixes in TopWiring

(cherry picked from commit b8a2dee2)

[F764.3] Add explicit SystemVerilogCompiler class

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit a564d73f)

(cherry picked from commit cf6402e1)

Previously, mems marked no dedup would prevent mems with the same
instance name in other modules from deduping

(cherry picked from commit abaa38f4)

This adds an apply method to the LogLevel object for conversion from a
String to a LogLevel.value.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit ba2bbc74)