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freechipsproject
firrtl
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firrtl-fix-asyncreset-emission
952bf381
·
Update constant assignment of async reset to not be inferred as a latch, works with donttouch
·
Feb 05, 2020
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azidar-patch-2
8b38150e
·
Create scala.yml
·
Jan 24, 2020
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case
71fa93f0
·
[wip] case emission for registers
·
Jan 06, 2020
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improve-infer-resets
a2e6b4f9
·
Minor code cleansup in InferResets
·
Dec 27, 2019
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improve-infer-resets-rc
9dc8e7f4
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Minor code cleansup in InferResets
·
Dec 27, 2019
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mangle-target-dir
ea0879f0
·
"cd subdirectory" for each stage
·
Dec 10, 2019
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dont-serialize
fef4da9b
·
DontSerialize Circuit, Emitted Annotations
·
Dec 06, 2019
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issue-1261
3438b180
·
Make WriteEmitted an Identity Phase
·
Dec 03, 2019
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chain-verilog-opts
f8fedc33
·
WIP on chaining some VerilogEmitter optimization transforms
·
Dec 02, 2019
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cleanup-verilog-emitter-casts-1.2.0
b2a3bb63
·
Remove unnecessary $signed casts for PrimOps in Verilog Emitter
·
Nov 30, 2019
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formatted-1
0e8add2b
·
Merge remote-tracking branch 'origin/formatted-1-se' into formatted-1
·
Nov 13, 2019
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graal-native-image
220be5f2
·
Add Makefile rules to build native image
·
Nov 09, 2019
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improve-squash-empty
756444ba
·
Squash empty in DCE
·
Nov 04, 2019
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squash-empty-proof-of-concept
71d27f20
·
Only remove empty statements in Block.mapStmt
·
Nov 01, 2019
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squash-empty
8f5969ac
·
WIP fix tests
·
Nov 01, 2019
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fix-chirrtl-mem-ren-on-reference
8582c65d
·
Fix handling of read enables in RemoveCHIRRTL
·
Oct 24, 2019
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clock-boundary
66c3b8b6
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Merge branch 'master' into clock-boundary
·
Sep 24, 2019
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mybranch
991ab2b1
·
Update Driver documentation
·
Sep 19, 2019
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upstream-intervals-2
12252c9e
·
This is a merge between the upstream-intervals and master
·
Sep 15, 2019
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promote-submodule-low-firrtl
47cc25e9
·
Allow delimiter to change in PromoteSubmoduleAnnotation
·
Aug 30, 2019
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