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freechipsproject
firrtl
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1.6-release
54f3f027
·
Bump version strings.
·
Apr 14, 2023
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1.5.x
39b68b3b
·
Make return value of Serializer.lazily lazy (#2627) (#2628)
·
Mar 21, 2023
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1.6.x
57b8a395
·
Make return value of Serializer.lazily lazy (#2627)
·
Mar 20, 2023
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actions/workflows/update-mergify
2be00274
·
Update .mergify.yml
·
Mar 15, 2023
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master-deprecated
45755184
·
Merge pull request #2613 from chipsalliance/maintenance-mode
·
Mar 15, 2023
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mergify/bp/1.4.x/pr-2588
fcf907a8
·
Fix invalid references generated by VerilogMemDelays (#2588)
·
Feb 03, 2023
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check-stderr-for-assertion-failure
b4c3a06a
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scalafmt
·
Jan 19, 2023
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cusotm-file-emission-replacements-only
ff3c3a14
·
CustomFileEmission: allow replacements to be used without emitting a file
·
Jan 17, 2023
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dated-snapshot
d2a9c9be
·
Restore publishing to be gated by push event
·
Jan 12, 2023
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1.5-release
b4054c2f
·
Merge branch '1.5.x' into 1.5-release
·
Jan 08, 2023
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1.4.x
486194c4
·
Fix optimization of register with reset but invalid connection (#2520) (#2522)
·
Apr 22, 2022
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mergify/bp/1.3.x/pr-2520
816df140
·
Fix optimization of register with reset but invalid connection (#2520)
·
Apr 22, 2022
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1.3.x
2ff74ab1
·
Fix incorrect deprecation warning for TargetDirAnnotation (backport #2511) (#2512)
·
Apr 11, 2022
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fix-memconf-port-order
19ffe6eb
·
Add another comment
·
Apr 05, 2022
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mergify/bp/1.4.x/pr-2485
cb608b26
·
Fold VerilogModulusCleanup into LegalizeVerilog (#2485)
·
Mar 02, 2022
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mlir
a53a3685
·
wip
·
Jan 31, 2022
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mutablerenamemap
d5ba5d24
·
Turn RenameMap into a trait and add MutableRenameMap
·
Dec 14, 2021
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fewer-verilog-submodule-port-wires
2db3cf41
·
WIP On emitting fewer worthless wires for submodule ports
·
Dec 13, 2021
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gtkwave
d7db4263
·
Add CustomRadixGTKWaveAnnotation to generate Tcl script for GTKWave.
·
Dec 05, 2021
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remove_deprecated_9
6b942e0f
·
remove firrtl.stage.transforms.CheckScalaVersion.
·
Nov 21, 2021
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