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freechipsproject
firrtl
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parallel-anno-seq
33507720
·
WIP remap annotations in parallel
·
Jan 28, 2021
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mergify/bp/1.3.x/pr-2058
a00b6f31
·
Stop padding multiply and divide ops (#2058)
·
Jan 29, 2021
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fix-snapshot-publishing
d546e93d
·
Publish SNAPSHOTs on PRs as well
·
Jan 19, 2021
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dev/seldridge/verilog-modulus-fix
cf78737d
·
Fix VerilogModulusCleanup bug for SInt Remainder
·
Jan 11, 2021
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1.3-release
ffa1069f
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Merge branch '1.3.x' into 1.3-release
·
Dec 29, 2020
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1.2-release
e6bf498c
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removed scm info, because it gets sucked in by sbt-ci-release plugin
·
Dec 22, 2020
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expand-chisel-rvalue-sinks
536ffc18
·
[wip] Checkpoint commit
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Dec 18, 2020
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eliminate-target-paths-bug
0ace98ca
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Merge branch 'master' into eliminate-target-paths-bug
·
Dec 07, 2020
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parse-time
bcf54e24
·
Add serialization time to -ll info
·
Nov 18, 2020
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emit-annotations-single-target
ce982080
·
Make EmittedAnnotation a SingleTargetAnnotation
·
Oct 06, 2020
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improve-annotation-trace-logging
374d504d
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Improve trace logging of annotations
·
Sep 11, 2020
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flatten-module-with-no-instances-se3
de31b74f
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Mea culpa
·
Aug 28, 2020
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flatten-module-with-no-instances-se2
c3edb0c1
·
Simplify rename logic in InlineInstances
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Aug 28, 2020
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flatten-module-with-no-instances-se
aa3c80e6
·
Fix problem when flattening/inlining a lone module
·
Aug 26, 2020
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uint-lower-types
6e01592d
·
Add CollapseVectors to LoweringCompilers
·
Aug 17, 2020
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no-chirrtl
f5d1fbd6
·
WIP on removing behavioral mems after ExpandWhens
·
Aug 13, 2020
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remove-x-optimism
40a3c93f
·
Fix handling of X optimism for memories
·
Aug 04, 2020
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format-src
d71e45d4
·
Oops, adding .scalafmt.conf
·
Aug 04, 2020
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bye-bye-chirrtl
5cf450f3
·
Add new pass to remove behavioral memory accesses
·
Aug 03, 2020
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dependency-order-improvement
0a31b0ed
·
[wip] Add Chisel proxy example
·
Jul 30, 2020
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