Fold VerilogModulusCleanup into LegalizeVerilog (#2485)

This fixes handling of signed modulus and removes some redundant work.

(cherry picked from commit 95cae3cd)

# Conflicts:
#	src/main/scala/firrtl/backends/verilog/LegalizeVerilog.scala
#	src/test/scala/firrtlTests/VerilogEquivalenceSpec.scala