(cherry picked from commit 4f1f4a77)

# Conflicts:
#	src/test/scala/chiselTests/Mem.scala
#	src/test/scala/chiselTests/util/SRAMSpec.scala

* Report source locator in when scoping error messages (#3804)

(cherry picked from commit d21a6635

)

# Conflicts:
#	core/src/main/scala/chisel3/Data.scala

* resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix Reg() to properly handle clocks as rvalues (#3775)

Previously, it was not calling .ref. It was thus not properly:
1. Checking that the clock is bound hardware
2. Checking that the clock is visible in the current scope
3. Reifying the clock if its a view

Note that RegInit() was already correctly calling .ref.

(cherry picked from commit 1c348c55

)

# Conflicts:
#	src/test/scala/chiselTests/ClockSpec.scala

* Resolve backport conflicts

* fix test

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit d8991c55

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* Bump versions
* It now tabs every line included in the Release Notes section of
  the PR template

(cherry picked from commit b00b22a1

)

# Conflicts:
#	.github/workflows/config/release-notes.json
#	.github/workflows/release-notes.yml

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Aditya Naik <aditya.naik@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 24de2f28)

* Update Scala CLI Template (#3757)

* Use "dep" instead of deprecated "lib"
* Add _root_ to `import circt.stage.ChiselStage`
  * Also add comment describing how this disambiguates from
    chisel3.util.circt when the user does `import chisel3.util._`
* Bump versions in Github workflows

(cherry picked from commit 589f1067

)

# Conflicts:
#	.github/workflows/build-scala-cli-template.yml
#	.github/workflows/build-scala-cli-template/chisel-template.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Support === on empty Aggregate (#3747)

(cherry picked from commit da6ae7dc

)

* Fix for Scala 2.12

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Don't emit nodes when calling .asBool on a Bool

(cherry picked from commit d5e65a33

)

# Conflicts:
#	core/src/main/scala/chisel3/Bits.scala
#	src/test/scala/chiselTests/LTLSpec.scala
#	src/test/scala/chiselTests/VerificationSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

This fixes Scala compiler warnings in Scala 2.13.12 requiring type
ascriptions on public implicit definitions.

(cherry picked from commit d011b443

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* bug fix for decoderbundle not being able to be lhs op

* add default field for DecodeField for DecodeTable non X case

* add test to show DecodeField default use case

(cherry picked from commit 7466789a

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit e6c07b37

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 1ae807ac

)

Co-authored-by: Mads Rumle Nordstrøm <85681203+madsrumlenordstrom@users.noreply.github.com>

(cherry picked from commit 53a86258

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Sanitize Record._elements (#3419)

This moves name sanitation a little earlier and ensures that the
sanitized names are use more consistently throughout Chisel internals.

This fixes a bug in D/I where unsanitary names would lead to a crash.

(cherry picked from commit 5c282db5

)

* Keep Scala 2.12 support by not using VectorMap

* Fix firrtl in tests for older firrtl spec version

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* SRAM API: Add multiple-clocked port API (#3383)

This PR adds new APIs for the SRAM module to instantiate a number of ports connected to individual clocks. This allows the creation of memories driven by multiple clocks, for use cases like clock domain crossover.

(cherry picked from commit d79ae71e

)

---------

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jared Barocsi <jared.barocsi@sifive.com>

* Deprecate calling .viewAs on non-hardware (#3395)

It's an error in most cases already, and in the cases it isn't, make it
a warning. Also fix a crash that could occur when viewing a non-Data
containing non-hardware Data.

(cherry picked from commit 1e524de9

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/DataView.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

This is not a functional bug. The recursive form of reify for Element
would use the .topBinding from the wrong argument, so it would recurse
an extra time, but it would ultimately converge to the right value.

(cherry picked from commit 374b45b9

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Support literals and DontCare in DataView targets (#3389)

(cherry picked from commit 0f803cd8

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/DataView.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* log2 functions
* unsignedBitLength

(cherry picked from commit 88fecfc1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 2e95804f

)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>

Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (#3361)

* Implement a SyncReadMem wrapper with explicit read, write, and readwrite ports (#3228)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 8851faed

)

* Delete typeName def

---------

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jared Barocsi <jared.barocsi@sifive.com>

(cherry picked from commit b83f3695

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 308eb6a4

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

This enables Chisel users to use these newer Scala versions.

(cherry picked from commit b22c3ba2

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit e20a0380

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Don't emit implicit clock warnings for `SyncReadMem.readWrite` when explicit clocks are used (backport #3313) (#3315)

* Don't emit implicit clock warnings when an explicit clock is used (#3313)

(cherry picked from commit 9e392013

)

# Conflicts:
#	core/src/main/scala/chisel3/Mem.scala

* Resolve backport conflicts

---------

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Optimize BitPat equals, overlap, and cover (#3285)

(cherry picked from commit f590ac9f

)

* Fix binary compatibility issue

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

This does not seem to be required by Scala, but it is required by newer
versions of SemanticDB (and thus to use Scala Metals).

(cherry picked from commit 08369ef8

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit b542b6ab

)

Co-authored-by: Sihao Liu <sihao@cs.ucla.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Change what DataView allows in its type checking to enable Reset to be
viewed as either a UInt<1> or an AsyncReset.  This enables more flexible
DataViews which match already allowable Chisel and FIRRTL connection
semantics.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 44ce96cf

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add new workflow to fixup backports for release notes (#3252)

The Mergify-generated backports do not currently include the information
needed by the release notes generation automation. This new workflow
will copy such information over to backport PRs.

(cherry picked from commit 86ccd1b2)

* Fix backport-fixup for labels with spaces (#3255)

(cherry picked from commit 8f7e7e68

)

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 7b57e591

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit bc4d8f9a

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Implement read-write memory accessors for SyncReadMem (#3190)

Adds new APIs to generate explicit read-write (rdwr) ports for a SyncReadMem, and all masked or clocked variants.
---------

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 1e6f2b4e

)

* Add CompileOptions to SyncReadMem.readWrite methods

---------

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Change many tests from simulation-based to checking the CHIRRTL.
* Move tests that were hard to convert to new VecIntegrationSpec in
  integration-tests

(cherry picked from commit 6b81f44c

)

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

(cherry picked from commit 8ca8b2e1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Read previousVersions for bincompat checking from a file (#3202)

This makes it much easier to automate checking new versions as they are
released.

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 2c6028b0

)

# Conflicts:
#	build.sbt

* Enable binary compatibility checking against 3.6.0

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

This adds a new Chisel template for using Chisel with Scala CLI, and
adds some automation for uploading versions of this template on tagged
releases (or workflow dispatch).

(cherry picked from commit 20246185

)

Co-authored-by: Jack Koenig <koenig@sifive.com>