- Mar 19, 2021
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mergify[bot] authored
Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a Verilator simultation issue in top.cpp where the eval() function is only called once per simultation loop. If the clock and reset are both changed and eval() is only called once, then any combinational update due to a change in reset is not visible to the sequential logic. This avoids issues where the downstream compilation utilities move synchronous reset logic outside of an always block that describes a synchronous reset flip flop. Reset now deasserts on time unit 10 and the clock ticks on time unit 11. h/t @albert-magyar Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit ac094a5e ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Mar 18, 2021
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mergify[bot] authored
Change a test to use emitChirrtl instead of emitFirrtl. This test isn't supposed to be running the Scala FIRRTL Compiler, but the latter method causes this to happen. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 492a71d6 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Mar 14, 2021
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mergify[bot] authored
* [plugin] Split ChiselComponent into its own file (cherry picked from commit e80e9a3b) * [plugin] Implement autoclonetype in the compiler plugin (cherry picked from commit 14942312) * [plugin] Stop autoclonetype stack traces when using plugin The compiler plugin obviates the need for using stack traces to determine outer objects in autoclonetype. When the plugin was used to compile a given Bundle, it will no longer collect a stack trace upon construction. This should have massive benefits to elaboration runtime. (cherry picked from commit a8d32388) * [plugin] Disable BundleComponent by default, add option to enable (cherry picked from commit 3bea6167 ) * Fix plugin scalacOptions for 2.11 * allowReflectiveAutoCloneType must work outside of Builder context Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Mar 13, 2021
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Jack Koenig authored
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- Mar 12, 2021
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mergify[bot] authored
This annotation adds memory import with inline generation for the emmiter. Supports both readmemh and readmemb statements based on argument. (cherry picked from commit 9ea57e03 ) Co-authored-by:
Carlos Eduardo <carlosedp@gmail.com>
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- Mar 04, 2021
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mergify[bot] authored
(cherry picked from commit 36e72239 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Mar 03, 2021
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mergify[bot] authored
* Adding ChiselEnum Documentation Entry Added documentation for the ChiselEnum type with verified examples * Fixed some doc ambiguity and repeated emitVerilog calls * Added ChiselStage and commented out package definition since packages cannot be declared in single files * Fixed issue with ChiselStage not being able to generate a module with parameters and bad package imports * Opps on not adding _ after import * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Modified Bundle for ci and made changes to select naming scheme * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Added missing backticks * Added space around error block quote * Fixed md paragraph in code * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Fixed some comments and formatting Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> (cherry picked from commit 73184b73 ) Co-authored-by:
chrisbaldwin2 <75344803+chrisbaldwin2@users.noreply.github.com>
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- Mar 02, 2021
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mergify[bot] authored
Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 43de37fd ) Co-authored-by:
Jerry Zhao <qwertyuiopghb@gmail.com>
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- Feb 24, 2021
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mergify[bot] authored
Not a Pokémon (cherry picked from commit c2ba4098 ) Co-authored-by:
edwardcwang <edwardcwang@users.noreply.github.com>
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- Feb 11, 2021
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Schuyler Eldridge authored
* Handle MemTypeBinding in Analog Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * Fix stack trace trimming across ChiselStage Fix bug in stack trace trimming behavior. Now, the following is what happens: 1. The Builder, if catching accumulated errors, will now throw a ChiselException with a Scala-trimmed Stack trace. Previously, this would throw the full excpetion. 2. The Elaborate phase handles stack trace trimming. By default, any Throwable thrown during elaboration will have its stack trace *mutably* trimmed and is rethrown. A logger.error is printed stating that there was an error during elaboration and how the user can turn on the full stack trace. If the --full-stacktrace option is on, then the Throwable is not caught and only the first logger.error (saying that elaboration failed) will be printed. 3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain all inherit the behavior of (2). Mutable stack trace trimming behavior is moved into an implicit class (previously this was defined on ChiselException only) so this can be applied to any Throwable. No StageErrors are now thrown anymore. However, StageErrors may still be caught by ChiselMain (since it is a StageMain). Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test all this behavior. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * Fix stack trace trimming in Driver Fix bug in stack trace trimming behavior. The Driver will now handle fake stack trace printing to standard out directly instead of this happening someplace else and relying on StageError to communicate "fail immediately" behavior. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Jack Koenig authored
* Add no-plugin-tests for testing Chisel without the compiler plugin This is a new SBT build unit that symlinks in some files from the normal chisel project tests, but builds them without the compiler plugin. (cherry picked from commit 53b62047) * Make it possible to GC Data instances No longer create a pointer from parent to every HasId, only do it by default for BaseModules and MemBases. Add pointer from parent to Data upon binding the Data. * Add MemTypeBinding for port types of Mems This binding is similar to the SampleElementBinding for Vecs in that these Data are not truly hardware, but are represented in the FIRRTL IR and thus need some representation. * Call _onModuleClose on unbound Records This maintains some corner-case behavior that is nevertheless relied upon. It ensures that refs are set for the elements of Records, even if they are not bound to any real hardware. (cherry picked from commit 0a0d7c6a)
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- Feb 06, 2021
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mergify[bot] authored
Signed-off-by:
Jean Bruant <jean.bruant@ovhcloud.com> (cherry picked from commit e3b6cf4e ) Co-authored-by:
John's Brew <46595442+johnsbrew@users.noreply.github.com>
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- Feb 05, 2021
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mergify[bot] authored
* Fix some botched formatting (replace ```mdoc scala with ```scala mdoc) * Replace some unnecessary uses of triple backticks with single backticks * Move appendix docs from wiki-deprecated/ to appendix/ * This will require an update on the website as well * Update Bundle literal docs (cherry picked from commit 8fa46071 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Feb 02, 2021
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mergify[bot] authored
* Update reported width from div/rem to match FIRRTL results * Add tests for width of % and / on UInt and SInt * Add loop-based test for known UInt/SInt op result widths Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit 98ce9194 ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> Co-authored-by:
Jack Koenig <koenig@sifive.com>
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Jack Koenig authored
* Bump to Scala 2.12.13 (#1766) (cherry picked from commit 445b5cec) * Fix chisel3-plugin binary compatibility checking chisel3-plugin not yet published for Scala 2.12.13, check binary compatibility with Scala 2.12.12 instead.
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- Jan 27, 2021
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mergify[bot] authored
If a method passed to higher function does not return any value, it is prefer to use `foreach` instead of `map`. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 654db98e ) Co-authored-by:
SoyaOhnishi <ohnishi.soya@arc.cs.okayama-u.ac.jp>
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mergify[bot] authored
(cherry picked from commit d0db0b8b ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jan 25, 2021
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mergify[bot] authored
This is a nit fix. no logic is changed. * Rename `typeName` to `enumTypeName` in ScalaDoc * Add return type at public method * Rename `enum_records` into `enumRecords` to retain name consistency Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit 2a967670 ) Co-authored-by:
SoyaOhnishi <ohnishi.soya@arc.cs.okayama-u.ac.jp>
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- Jan 23, 2021
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mergify[bot] authored
(cherry picked from commit e63b9667 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jan 20, 2021
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mergify[bot] authored
This is useful for libraries to guard operations implemented via annotations or BlackBoxes by the current when predicate (cherry picked from commit cdb7bb27 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jan 11, 2021
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mergify[bot] authored
Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (#1714) (#1721) * Add (failing) Test for Data toTarget calls Add scaladoc and clean up test * Builder: don't let .toTarget pass if it won't be able to deserialize properly later * Update src/test/scala/chiselTests/ReferenceTargetSpec.scala * Rename and simplify tests for literal toTarget (cherry picked from commit b578aa5e ) Co-authored-by:
Megan Wachs <megan@sifive.com>
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- Dec 18, 2020
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mergify[bot] authored
(cherry picked from commit a600a95b ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Remove CircleCI (#1702) Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit eae69e95 ) # Conflicts: # .circleci/config.yml * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Dec 17, 2020
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mergify[bot] authored
* Switch to using Github Actions CI (#1690) MiMa binary compatibility checks are now run on master, but the mimaPreviousArtifacts are empty which makes the check a no-op. This helps keep both the build.sbt and CI more consistent between master and stable branches. .mergify.yml is also updated with mergify.sc from chisel-repo-tools using the following configuration: conditions: - status-success=all tests passed branches: - 3.2.x - 3.3.x - 3.4.x (cherry picked from commit 25a417f8 ) # Conflicts: # .mergify.yml # build.sbt # project/plugins.sbt * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Dec 09, 2020
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mergify[bot] authored
- fix build.sbt - fix build.sc (cherry picked from commit 315ff8c6 ) Co-authored-by:
Chick Markley <chick@qrhino.com>
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- Dec 08, 2020
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mergify[bot] authored
* Builder: use LazyLogging.logger.warn to print elaboration message * add deprecation for chisel3.internal.ErrorLog.info. * add test to check elaboration message still exist. Co-authored-by:
Kevin Laeufer <kevin.laeufer@sifive.com> (cherry picked from commit e8f90ef5 ) Co-authored-by:
Jiuyang Liu <liu@jiuyang.me>
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- Dec 02, 2020
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mergify[bot] authored
(cherry picked from commit ba05dcaf ) Co-authored-by:
Kevin Laeufer <electron.kiwi@gmail.com>
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- Nov 24, 2020
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mergify[bot] authored
(cherry picked from commit e11d8b85 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 12, 2020
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mergify[bot] authored
(cherry picked from commit e6192ea7 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 11, 2020
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mergify[bot] authored
* Refine autonaming to have more intuitive behavior (#1660) * Refine autonaming to have more intuitive behavior Last name in an Expression wins, while the first Statement to name wins. This is done via checking the _id of HasIds during autonaming and only applying a name if the HasId was created in the scope of autonaming. There is no change to .autoSeed or .suggestName behavior. Behavior of chisel3-plugins from before this change is maintained. * Update docs with naming plugin changes (cherry picked from commit 1260f7c8 ) * Waive binary incompatibility false positive in 2.11 Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
The SecurityManager is global so is not thread-safe. This is the source of flaky tests in FIRRTL CI. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 9f1d6cbb ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 06, 2020
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mergify[bot] authored
This is a refinement of the assertion added in #1616 then removed in #1654. Because Records now set the refs of children upon binding, later, unbound Records could incorrectly override the refs. The first set should win. (cherry picked from commit 8187318e ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Remove Data.setRef assertion (#1654) It causes issues for some legal (if awkward) patterns. A larger refactor of when refs are set could reinstate this check. (cherry picked from commit 679dd54a ) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Fix merge conflict Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 03, 2020
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mergify[bot] authored
Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 70538487 ) Co-authored-by:
John Ingalls <43973001+ingallsj@users.noreply.github.com>
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mergify[bot] authored
* Bugfix - adding external modules was broken (#1649) (cherry picked from commit d21fe713 ) * Remove test because not backportable * Remove extra space Co-authored-by:
Adam Izraelevitz <azidar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* ExtModule's lacked support built in support for providing the verilog source. This changes creates traits that can be used with ExtModule to provide the support currently found in BlackBox - Add support for ExtModule helpers - HasExtModuleResource to use addResource - HasExtModuleInline to use setInline - HasExtModulePath to use addPath - Add tests of the above support. - Note: These tests use Stage instead of Driver - Added ScalaDoc for HasBlackBoxInline#setInline * Fix the danged trailing commas. * Change to use `.transform` as the correct API for `ChiselStage` (cherry picked from commit fd92809e ) Co-authored-by:
Chick Markley <chick@qrhino.com>
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- Oct 31, 2020
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mergify[bot] authored
This requires a combination of things, but it happens to be a combination used by Diplomacy in Rocket Chip. It must be a Record in compatibility code with Vecs as fields and a mix of components with and without set directions. (cherry picked from commit 0979133b ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 28, 2020
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mergify[bot] authored
(cherry picked from commit 362a3e35 ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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- Oct 27, 2020
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mergify[bot] authored
* Fix crosslinks in mdoc. Can't use md suffix * Removed all .md crossrefs Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 58fa3c11 ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Use Data refs for name prefixing with aggregate elements (#1616) * Use Data refs for name prefixing with aggregate elements Vecs set the refs of their elements upon construction of those elements. In the past, Records haven't set their elements refs until module close, but it can be done sooner. Doing it upon binding means that refs will at least be available for Records used in hardware elements. Since only bound Data can be connected to anyway, Aggregate elements being connected to will always have a ref which we can then use for creating naming prefixes. * Add tighter correctness checks * Handle more cases in connection prefixing Add support for forcing setRef to override a previous setting. This is only used by BlackBox ports which need to drop their io prefix. Also add a Try() around Data.bindingToString which sometimes throws exceptions when being used to .toString a Data in an error message. * Strip trailing spaces in names in compiler plugin (cherry picked from commit 0745dede ) * Resolve binary compatibility issues Change to Builder.scala is cleaner than waiving all of the (safe to waive) failures. Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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