This does not seem to be required by Scala, but it is required by newer
versions of SemanticDB (and thus to use Scala Metals).

* Update upickle to 3.1.0
* Update os-lib to 0.9.1

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

- Enable .viewAsSupertype to work on Records
- fix a nondeterminism error in DataView noticeable on error reporting

Enable a user to define Scala-time properties on an Interface.  These
properties require a conformance to examine.  This enables patterns where
a client wants to configure itself based on knowledge of the component,
e.g., when the client is a testbench.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Make the frequency a legal value (14 days).

Fix a bug in naming where a Module that took a Unit parameter could cause
naming to crash.  This is, admittedly, a very weird pattern, but can occur
if you have a type-parametric module where certain type parameterizations
can be Unit.

Fix #3245.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix a bug in the new BoringUtils.bore API where this would generate
invalid FIRRTL if the user did boring which created a path that went up to
an LCA and then down.  Change the internal leastCommonAncestor utility to
also return the LCA module as this avoids a second call to compute the
LCA.

Fixes #3239.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change what DataView allows in its type checking to enable Reset to be
viewed as either a UInt<1> or an AsyncReset.  This enables more flexible
DataViews which match already allowable Chisel and FIRRTL connection
semantics.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

The Mergify-generated backports do not currently include the information
needed by the release notes generation automation. This new workflow
will copy such information over to backport PRs.

* Mark generated wires for read and readWrite as temporary
* Remove semicolons
* Remove intermediate wire for read/readWrite port address
* Convert usages of UnlocatableSourceInfo into macro applications

* Add .unsafe to connectables

* Added .as and .squeezeAllAs to connectable

* Make connectable exceptions error at end of elaboration

Bump firtool version to get parsing of new connect/invalidate
statements.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix a bug where the name of the Stub module (a module auto-generated from
an Interface without an implementation available) would be called "Stub"
as opposed to the name of the Interface.  This could create a linker error
if the Stub was used.

Fix this setting the final "desiredName" inside the Entity.  Add a test that
this works for the Stub.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add the `circt.clock_gate` intrinsic. This is not yet used anywhere and
has no impact on existing code. Also move CIRCT-specific tests into a
`circt` subpackage of `chiselTests.util` to reflect the main package
structure.

Change an abstract def to a val when specifying the ports of an
Interface.  This improves the static nature of the Interface and prevents
abuse as leaving this a s a def (a function) makes it a generator.

h/t @azidar

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Added skipPrefix and tests

* Added MatchesOrOmits

* Support BoringUtils in chisel internally, with tests

Migrate work from seldridge/chisel-separable on separate compilation
into upstream Chisel.  This defines an Interface and a Conformance.  An
Interface is a Singleton Object that maps to a FIRRTL external module
with pre-defined IO.  A Conformance is a type-class whose
implementations define how a Chisel module aligns itself to the
Interface.  Used together, these enable separate compilation of a client
that uses an Interface from a component that implements the Interface.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This makes it much easier to automate checking new versions as they are
released.

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Adds new APIs to generate explicit read-write (rdwr) ports for a SyncReadMem, and all masked or clocked variants.
---------

Co-authored-by: Megan Wachs <megan@sifive.com>

This utility provides a way to check different versions of type
equivalence in Chisel internals and generates error messages for when
mismatches are found. Specifically, it handles structural vs. nominal
typing as well as strict vs. non-strict width checking.

This adds a new Chisel template for using Chisel with Scala CLI, and
adds some automation for uploading versions of this template on tagged
releases (or workflow dispatch).