* Adding ChiselEnum Documentation Entry

Added documentation for the ChiselEnum type with verified examples

* Fixed some doc ambiguity and repeated emitVerilog calls

* Added ChiselStage and commented out package definition since packages cannot be declared in single files

* Fixed issue with ChiselStage not being able to generate a module with parameters and bad package imports

* Opps on not adding _ after import

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Modified Bundle for ci and made changes to select naming scheme

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Added missing backticks

* Added space around error block quote

* Fixed md paragraph in code

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/chisel-enum.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Fixed some comments and formatting

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Not a Pokémon

* Handle MemTypeBinding in Analog

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fix stack trace trimming across ChiselStage

Fix bug in stack trace trimming behavior. Now, the following is what
happens:

1. The Builder, if catching accumulated errors, will now throw a
   ChiselException with a Scala-trimmed Stack trace. Previously, this
   would throw the full excpetion.
2. The Elaborate phase handles stack trace trimming. By default, any
   Throwable thrown during elaboration will have its stack
   trace *mutably* trimmed and is rethrown. A logger.error is printed
   stating that there was an error during elaboration and how the user
   can turn on the full stack trace. If the --full-stacktrace option
   is on, then the Throwable is not caught and only the first
   logger.error (saying that elaboration failed) will be printed.
3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain
   all inherit the behavior of (2).

Mutable stack trace trimming behavior is moved into an implicit
class (previously this was defined on ChiselException only) so this
can be applied to any Throwable.

No StageErrors are now thrown anymore. However, StageErrors may still
be caught by ChiselMain (since it is a StageMain).

Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test
all this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Make Data GC-able

No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.

* Add MemTypeBinding for port types of Mems

This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.

* Call _onModuleClose on unbound Records

This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.

This is a new SBT build unit that symlinks in some files from the normal
chisel project tests, but builds them without the compiler plugin.

* Added SyncReadMem-based implementation of the Queue class

* Rework of the parametrized Queue class SyncReadMem-based implementation

* Modification of the parametrized Queue class SyncReadMem-based implementation

* Limiting the visibility of the read address for SyncReadMem-based Queue

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>

* Fix some botched formatting (replace ```mdoc scala with ```scala mdoc)
* Replace some unnecessary uses of triple backticks with single
  backticks
* Move appendix docs from wiki-deprecated/ to appendix/
  * This will require an update on the website as well
* Update Bundle literal docs

* Update reported width from div/rem to match FIRRTL results

* Add tests for width of % and / on UInt and SInt

* Add loop-based test for known UInt/SInt op result widths

Co-authored-by: Jack Koenig <koenig@sifive.com>

If a method passed to higher function does not return any value,
it is prefer to use `foreach` instead of `map`.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This is a nit fix. no logic is changed.

* Rename `typeName` to `enumTypeName` in ScalaDoc
* Add return type at public method
* Rename `enum_records` into `enumRecords` to retain name consistency

Co-authored-by: Jack Koenig <koenig@sifive.com>

Remove "val io" and rename MultiIOModule to Module

Co-authored-by: Megan Wachs <megan@sifive.com>

Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.

Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.

Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox

This PR revert #1480, but keep the test.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This is useful for libraries to guard operations implemented via
annotations or BlackBoxes by the current when predicate

Farewell Scala 2.11

* Add (failing) Test for Data toTarget calls

Add scaladoc and clean up test

* Builder: don't let .toTarget pass if it won't be able to deserialize properly later

* Update src/test/scala/chiselTests/ReferenceTargetSpec.scala

* Rename and simplify tests for literal toTarget

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

MiMa binary compatibility checks are now run on master, but the
mimaPreviousArtifacts are empty which makes the check a no-op. This
helps keep both the build.sbt and CI more consistent between master and
stable branches.

.mergify.yml is also updated with mergify.sc from chisel-repo-tools
using the following configuration:

conditions:
  - status-success=all tests passed
branches:
  - 3.2.x
  - 3.3.x
  - 3.4.x

- fix build.sbt
- fix build.sc

* Builder: use LazyLogging.logger.warn to print elaboration message

* add deprecation for chisel3.internal.ErrorLog.info.

* add test to check elaboration message still exist.

Co-authored-by: Kevin Laeufer <kevin.laeufer@sifive.com>

Implemented by folding Element.ref into Data.ref. Element.ref had
special handling for literals, but because Bundles can also be literals,
there were code paths that tried to get the ref of a Bundle literal
which was non-existent. Now, all literals are handled together.

Because FIRRTL does not have support for Bundle literals, Bundle literal
refs are implemented by materializing a Wire.