* Support === on empty Aggregate (#3747)

(cherry picked from commit da6ae7dc

)

* Fix for Scala 2.12

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 53a86258

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add messages to require statements in Math (#3385)

* log2 functions
* unsignedBitLength

(cherry picked from commit 88fecfc1

)

# Conflicts:
#	src/main/scala/chisel3/util/Math.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add Scala 2.13.11 and 2.12.18 to plugin cross versions (#3327)

This enables Chisel users to use these newer Scala versions.

(cherry picked from commit b22c3ba2

)

# Conflicts:
#	build.sbt

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Optimize BitPat equals, overlap, and cover (#3285)

(cherry picked from commit f590ac9f

)

* Fix binary compatibility issue

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix Printf macro to catch s-interpolator usages in Scala 2.13 (#3143)

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit f3d0f22d

)

# Conflicts:
#	core/src/main/scala/chisel3/Printf.scala
#	core/src/main/scala/chisel3/VerificationStatement.scala
#	docs/src/explanations/printing.md

* Resolve backport conflicts

---------

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit baed66d4

)

Co-authored-by: jensengrey <46599294+jensengrey@users.noreply.github.com>

* Use SourceInfo in Builder error messages when available (#2849)

* Use SourceInfo in Builder error messages when available

* Use line break instead of semicolon

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
(cherry picked from commit e45be10a

)

# Conflicts:
#	core/src/main/scala/chisel3/Module.scala
#	core/src/main/scala/chisel3/RawModule.scala
#	core/src/main/scala/chisel3/internal/Builder.scala

* Resolve backport conflicts

* Resolve binary compatibility issues

* Undo a change to a protected API
* Waive private classes (they're public in the bytecode because Java
  doesn't have a notion of file private)

* Fix test

---------

Co-authored-by: Daniel Resnick <danielzresnick@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* add curried MuxLookup.apply, deprecate old apply (#3095)

* overload MuxLookup.apply for EnumType
* remove MuxLookup.fromEnum
* add source locators to MuxLookup.apply using macros

(cherry picked from commit dcecabb6

)

* remove deprecated annotation, remove macro

---------

Co-authored-by: Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
Co-authored-by: Albert Chen <albert.chen@sifive.com>

* Fix FIRRTL spec emission and bump to spec 1.2.0 (#3094)

* Emit FIRRTL spec version in Emitter
* Bump FIRRTL spec version to 1.2.0

(cherry picked from commit 1ef1fc4e

)

# Conflicts:
#	firrtl/src/main/scala/firrtl/ir/Serializer.scala
#	firrtl/src/test/scala/firrtlTests/ExtModuleTests.scala
#	src/test/scala/circtTests/stage/ChiselStageSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* add MuxLookup.fromEnum

(cherry picked from commit 6dc2f58d)

* add example, better type signature

(cherry picked from commit c1b8e4c6

)

---------

Co-authored-by: Albert Chen <albert.chen@sifive.com>

(cherry picked from commit 4194e106

)

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>

Remove loadMemoryFromFile (and implicitly loadMemoryFromFileInline) from
the non-exhaustive list of deprecated things in the Roadmap.  This is
now planned to be supported by MFC [1].

[1]: https://github.com/llvm/circt/pull/4622



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit cdec8112

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

(cherry picked from commit b5e2a16d

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit e9917693

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix calculuation of firrtl directions for Vecs

For ports of type Vec, the direction of both the Vec itself and the
direction of its elements can affect the direction of the FIRRTL port.
Previously, we did not handle the fact that the Vec's elements could,
themselves, be Vecs, thus making this directionality calculation
recursive. Also, the logic was only applying to regular RawModules and
Modules. The fix now applies to BlackBoxes and ExtModules as well.

(cherry picked from commit b501b699)

# Conflicts:
#	core/src/main/scala/chisel3/RawModule.scala
#	src/test/scala/chiselTests/Direction.scala

* Fix calculation of firrtl directions for OpaqueTypes

Similarly to Vecs, both the direction of the OpaqueType itself and the
direction of its element can affect the direction of the resulting
firrtl port. Since OpaqueTypes can wrap other OpaqueTypes, this
direction calculation needs to be recursive. The same basic principle
applies to calculating firrtl flip for OpaqueTypes that are elements of
other Records.

(cherry picked from commit c4ec45b3

)

# Conflicts:
#	src/test/scala/chiselTests/RecordSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 040ba068

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* assert{Inferred,Known}Width: tweak to support width of zero.

Can't create -1.S(0.W), special-case zero-width.

* Bits: nicer error messages for zero-width

* Support zero-width integer literals.

These are in the FIRRTL language specification now
and supported by both SFC + MFC.

For SInt, special-case handle zero-width as not needing a sign bit.

Zero-width literals must be explicitly zero-width (`0.U(0.W)`);
literals such as `0.U` are (still) at least 1-bit.

* check zero-width to bool conversion

* onehot test

* UIntOps: test a few operations.

* SIntOps: test a few operations

* {S,U}IntOps: touchup test description, now includes head/tail/pad.

* ChiselSpec: Fix assert{Known,Inferred}Width for zero-width.

Specifically, fix the inferred-width check.

Start from zero-width literal, otherwise 0.U will need 1 bit.

* WidthSpec: update inferred zero-width test

(cherry picked from commit fc3b4a08

)

Co-authored-by: Will Dietz <will.dietz@sifive.com>

* TruthTable improvements: structural equality and delete sort (#2935)

We had implemented equals, but not hashCode. This commit also changes
the implemental of equals to just use the underlying values instead of
wasting the compute calling .toString.

Delete TruthTable.sort, it is unused.

(cherry picked from commit b5d9c08b

)

* Restore and deprecate TruthTable.sort

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Promote ChiselEnum user APIs from experimental (#2929)

They are commonly used and if we were ever to change them, we will need
to go through a deprecation process anyway.

Note that the EnumAnnotations remain in chisel3.experimental because,
like all Chisel annotation support, they are slated to be deprecated and
removed.

(cherry picked from commit 424e9446

)

# Conflicts:
#	docs/src/cookbooks/verilog-vs-chisel.md
#	docs/src/explanations/chisel-enum.md

* Maintain binary compatbility, use aliases in chisel3 package

* Deprecate the actual classes in chisel3.experimental
* Also fix backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Check for Vec subaccess in NamedComponent and throw a nicer error. (#2907)

This would previously end up throwing an exception later, when trying
to create a component name and realizing that it was invalid. Instead,
this detects Vec subaccesses early, and gives a more precise error and
suggestion.

(cherry picked from commit d8c30961

)

# Conflicts:
#	core/src/main/scala/chisel3/internal/Builder.scala

* Resolve backport conflicts

Co-authored-by: Mike Urbach <mikeurbach@gmail.com>

ChiselEnums check if they should create annotations every time an
instance of them is bound. Because so many annotations would be created,
they check to see if an equivalent annotation has already been added to
the annotations. Previously, this used a linear search of the
annotations, now it uses a HashSet.

(cherry picked from commit 96bde092

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit b91a2050

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* DRY out CI (#2903)

* Minor tweaks to setup-oss-cad-suite
* Switch espresso installation to composite action
* Switch circt installation to composite action

(cherry picked from commit dbd5f48a

)

# Conflicts:
#	.github/workflows/test.yml

* resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Switch from YosysHQ action to composite action (#2901)

The YosysHQ Github Action for setting up the OSS CAD Suite is very flaky
in CI so instead we can just wget and untar the suite ourselves. It also
seems prudent to try out composite actions to avoid duplication of
installation steps.

(cherry picked from commit 75aeaed9

)

# Conflicts:
#	.github/workflows/test.yml

* Resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix BitSet decoder API when errorBit=False

    When errorBit is set to False, the original code will return
    `Unit` which will be `()` in interpolated string.

* Add testcases for both errorBit cases in BitSetSpec

(cherry picked from commit 42416cb6

)

Co-authored-by: Ocean Shen <30361859+OceanS2000@users.noreply.github.com>

Co-authored-by: Aditya Naik <aditya.naik@sifive.com>

* [ci] Update Github Actions (#2876)

* Switch from deprecated setup-scala to setup-java
* Switch from deprecated set-output to $GITHUB_OUTPUT
* Use $GITHUB_STEP_SUMMARY for reporting

(cherry picked from commit b01dd3cb

)

# Conflicts:
#	.github/workflows/test.yml

* Resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Make PriorityMux stack safe (#2854)

It used to be implemented with recursion, now it's implemented with a
stack safe reverse and foldLeft.

Also there were no tests for PriorityMux so I added one which helps
prove the change is functionally correct.

(cherry picked from commit 269ce472

)

# Conflicts:
#	src/test/scala/chiselTests/util/PipeSpec.scala

* Resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add versionScheme (PVP) to SBT publish settings (#2871)

This allows build tools to warn users about possible binary
incompatibility issues when using dependencies that depend on
mutually incompatible versions of Chisel.

(cherry picked from commit 9f080d51

)

# Conflicts:
#	build.sbt

* Resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Implement compressed Namespace (#2856)

The namespace disambiguates requests for the same name with _<idx>.
Rather than storing every disambiguated name in the underlying HashMap,
it now only stores the base along with the "next available" index. This
makes the logic for checking if a name is already contained in the
namespace slightly more sophisticated because users can name things in a
way that will collide with disambiguated names from a common substring.

For example, in naming the sequence "foo", "foo", "foo_1", the 2nd "foo"
takes the name "foo_1" so the following "foo_1" gets disambiguated to
"foo_1_1". But since we compressed that original "foo_1" into the same
HashMap entry as just "foo", we have to do a form of "prefix checking"
whenever naming something that ends in "_<idx>".

In practice, the saved memory allocations more than make up for the more
complicated logic to disambiguate names because the common case is still
fast.

(cherry picked from commit 1654d87a

)

# Conflicts:
#	core/src/main/scala/chisel3/internal/Builder.scala

* Resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 49feb083

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* Change RawModule._commands to a VectorBuilder (#2839)

* Change RawModule._commands to a VectorBuilder

Use the resulting Vector to build the underlying Component's commands
and then use those instead of copying the original ArrayBuffer when
iterating on commands. Previously, the Component was using a List to
hold the commands which is particularly memory inefficient, especially
for large modules.

* Optimize Converter's handling of Seq[Command]

It previously converted the Commands to a List (which, while not
captured in the type system, they were already a List) and then used
head and tail iteration. This is less efficient with the new underlying
Vector implementation.

(cherry picked from commit 48a1ef0a

)

* Waive false binary compatibility failures

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

(cherry picked from commit aa596b98

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* Add internal methods to maintain binary compatibility

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fixup and unit tests for D/I of IOs without explicit Input/Output (#2792)

(cherry picked from commit f24a6248

)

# Conflicts:
#	core/src/main/scala/chisel3/Module.scala

* Resolve backport conflicts

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Unify Chisel2 and chisel3 directionality (#2634)

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 1aea4ef9

)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala
#	core/src/main/scala/chisel3/Module.scala
#	src/test/scala/chiselTests/Direction.scala

* fix up backport

* fix up backport

* clean up diff

* make test order like it was on master

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>

* Switch to using experimental trait for OpaqueTypes (#2783)

This makes it more clear that the feature is experimental. Users may
still override the opaqueType method for more dynamic control over when
instances of a given Record are OpaqueTypes or not, but they are
discouraged from doing so.

(cherry picked from commit 7525dc71

)

* Fix cloneType in RecordSpec

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add Aggregate.elementsIterator and micro-optimize

elementsIterator provides a more efficient API for iterating on the
elements of Aggregates. It is especially useful for Records where
getElements returns a Seq and thus eagerly constructs a new
datastructure which may then just be iterated on anyway.

This new elementsIterator API is then used throughout the codebase where
it makes sense.

Also change Vec.getElements to just return the underlying self instead
of constructing a new Seq.

(cherry picked from commit defa440b)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala
#	core/src/main/scala/chisel3/Module.scala
#	core/src/main/scala/chisel3/experimental/Trace.scala

* Move Aggregate.bind inline into Record.bind

Vec overrides bind and does not call the version in Aggregate so the
version in Aggregate is misleading in that its only ever used by
Records. Now there is no version in Aggregate and the actual
functionality and use is more clear.

(cherry picked from commit b054c30b)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala

* Extract and optimize duplicate checking Record.bind

This replaces an immutable.Map with a single mutable.HashSet and saves
the allocation of # elements Seqs.

(cherry picked from commit 832ea52b)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala

* Add check for Records that define def elements

(cherry picked from commit a4f22341

)

* Resolve backport conflicts

* Make elementsIterator final and package private

* Waive false MiMa failure

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Bugfix converter clearing flips (#2788)

* Bugfix: Output on Vec of bundle with mixed field orientations
* Bugfix OpaqueTypes clearing flips

(cherry picked from commit f05bff1a

)

# Conflicts:
#	src/test/scala/chiselTests/Direction.scala

* Resolve backport conflicts

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>