* Moved CoreMonitorBundle class to util package

* adding cjtag

Respect SEIP during WFI clock gate

rename ahb_fuzzing plusarg

Add plusarg option to disable fuzzing

* adding registers to the OM

Minor QoR improvements

* changing where getOMComponents is called in the flow

s2_xcpt doesn't need to drive so many things.

Trace: suggestName trace node

Bump chisel3

Summary of changes:
* Basic BundleLiteral support
* Add lit*Option methods for extracting literals
* Improved numbering of _T_*
* Undeprecate log2Up and log2Down
* BoringUtils for synthesizable cross module references
* Seq[Data] illegal in Bundle, override with ignoreSeq
* MixedVec
* Module Inlining and Flattening Support
* Verilog memory loading
* Access module ports via DataMirror.modulePorts
* Support for .B on [Big]Ints
* Stack Trace Trimming
* toBool[s] -> asBool[s]
* Improved UInt.-% emission

Move tvec bit-zapping from D to Q

bumping riscv-tools to spike change

Reserve the PMP R=0 W=1 combination

This was a post-v1.10 amendment to the spec:

https://github.com/riscv/riscv-isa-manual/commit/059f64c941856f249d8a0647e23e150dbdb1f62c

This addresses a simulation-pessimism problem.  The synthesis result
will be the same either way.  Before, in simulation, the value held in
these registers prior to the first write might not have had the
appropriate bits zapped, because of random initialization.

Resolves #1752

* diamond-problem-fix

Bundle bridge trace interface

* adding dcache om when there is no tim

This reverts commit c69607cf.

Implement debug trigger-sharing and chain-limiting proposals