Bump chisel3

Summary of changes:
* Basic BundleLiteral support
* Add lit*Option methods for extracting literals
* Improved numbering of _T_*
* Undeprecate log2Up and log2Down
* BoringUtils for synthesizable cross module references
* Seq[Data] illegal in Bundle, override with ignoreSeq
* MixedVec
* Module Inlining and Flattening Support
* Verilog memory loading
* Access module ports via DataMirror.modulePorts
* Support for .B on [Big]Ints
* Stack Trace Trimming
* toBool[s] -> asBool[s]
* Improved UInt.-% emission