This reverts commit 5d0e853e.

This reverts commit 5d0e853e.

Add DescribedSRAM

Dmi write delay fix

Add InModuleBody API

Remove unnesessary VPI dependency from SimJTAG

Parameters are not needed to implement this method.
Sometimes you might not have any.

This new API is strictly more powerful as you can use it from
helper functions. The instatiate() API required you to put your
extra glue code in one place and it had to be in the LazyModule.

* Add LookupByHartId key to look up properties without breaking dedup

* Use LookupByHartId to avoid directly referencing RocketTilesKey

* Make lrscCycles a core-specific parameter

* Increase lrscCycles to work without branch prediction

Since an LR/SC sequence can have taken branches/jumps within the loop,
Rockets with no branch prediction can fail to meet the forward-progress
guarantee.  Increase the timeout to handle the case that all instructions
hit in the I$ but up to 14 of them are mispredicted branches.
(14 is 16 minus the LR and the SC instructions themselves.)

This bug has flown under the radar because most times we use the same
project for the config and the top.  However, in the case of shells, you use
the top=shell and config=design, which are usually in different projects.

diplomacy: add BundleBridge for cross-module bundles

This can be quite useful for plumbing IO from deep inside the hierarchy to
the top of the design.

Additional information found in the following discussion:

https://github.com/freechipsproject/rocket-chip/commit/41702a950f2fdc9a247b654869bff6a9389a9bb2#commitcomment-29219295

This will be necessary to be able to decouple the top 'shell' from the
internal 'design'.  The way this is going to work is that the 'shell'
creates Nodes for it's top-level IO which are then connected to arbitrarily
deep points in the design.

Factor out some generic code in HasRocketTiles

src/main/scala/rocketchip/Configs.scala should be src/main/scala/subsystem/Configs.scala now

The pipeline design is tightly coupled with that of Rocket, so it isn't
general enough to be in BaseTile.

This seems generic enough.

NBDcache now creates a RAM named data_array_nbdcache__ext instead of _T_39_ext