Co-authored-by: Jiuyang liu <liujiuyang1994@gmail.com>

Partially reverts #2836, but in such a way that it works with the new QMC.

* Use new Chisel Decoder API

* CSR: fix decode when using new Chisel API

When using new API, io.rw.addr << 20 would not match any entry in
decode_table.

e.g. When io.rw.addr[11:0] == "h102", after left shift 20 it would
become "h10200000", which wont match SRET ("h10200073") as defined
in Instructions.scala. Note, SRET is not defined with DontCare.

Magically, old API can work with this case, which should not.

In this fix the least significant 20 bits of decode_table keys
are dropped to match addr.

* Make Decode logic width-safe

This involves ensuring all BitPats that correspond to a particular
portion of the decoded result are of the same width. BitPats with no
"don't cares" can be zero padded to the common width. BitPats with "don't
cares" that are too small are an error.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Zenithal <i@zenithal.me>

hardcode reg_vsstatus.xs to zero/dirty

* Fix typo: priviledged -> privileged

This incurs a small breaking change, but can be easily fixed.

* Add comments to amba and tilelink modules and fix typos.

Bind Verilog path with EICG_wrapper

Update Instructions with riscv-opcodes 

configs: add WithHypervisor config

[AXISBundleBits] re-add clonetype override

* AXISBundleBits extends off BundleMap which is of type Record and therefore needs cloneType
* resolves a user issue that can be seen at the repo in this post after compiling the current main's rocket-jar:
* https://stackoverflow.com/questions/72043687/implementing-a-diplomatic-axi-stream-interface-in-chisel-bundlemap-clonetype-e

* git repo: https://github.com/jurevreca12/temp_dspblock_example


* git commit: aca81ab9df437e8cea7fa8abd361b6bab7f40326
* note: replace `lib/rocketchip.jar` with a compiled jar from main
* bug fixed by replacing that rocketchip.jar with the rocketchip.jar generated from the branch in this PR

Signed-off-by: Michael Etzkorn 明凯 <michael-etzkorn@sage.micro.com>

Allow forcing RocketTiles into independent PRCI group

remove objectmodule

Update IncoherentBusTopology to support multiclock and custom cloking

Update Instructions with riscv-opcodes

[Documentation] Note CRC's object explicit+1 notation

Co-authored-by: Jerry Zhao <qwertyuiopghb@gmail.com>

#2963 just so users can follow the CRC object's API a bit better. 


Perhaps #2960 should include a scala doc

Rocket already implemented NMI in #2711,
however, riscv-opcodes currently does not have NMI
as it is a WIP (See https://github.com/riscv/riscv-opcodes/pull/67)

To avoid generating Instructions.scala from a patched riscv-opcodes,
putting NMI related insts/CSRs into CustomInstructions is reasonable.

As standard instructions are synced from riscv-opcodes