* Revert "updating README examples with Make changes (#2322)"

This reverts commit 875dcd3e.

* Revert "fixing aspect generation (#2309)"

This reverts commit bbeb2578.

* Revert "separate generator behavior into phases (#2274)"

This reverts commit 9d997506.

prci: allow configurable ClockGroupDriver drive function

Qualify load and store watchpoints by instruction type

*  assertion for speculative fetch chicken bit

* removed the assertion as it may fail due to race condtion

APBToTL: Qualify address alignment assertion

in particular, handle the common failure scenario where an L1 DCache is added to a design with no cacheable memory region.

Tl vip2

Summary of changes in chisel3:
* Patch fix to https://github.com/freechipsproject/chisel3/issues/1109

Summary of changes in firrtl:
* Constant propagate binary operations with matching arguments
* Revert last connect semantics support in reset inference
* Fix reset inference for Resets that are only invalidated

Co-Authored-By: Jack Koenig <koenig@sifive.com>

Fix typos in Debug Module register descriptions.

Summary of changes:
* Fix := of DontCare to AsyncReset and Reset
* Boost performance of Vec cloning
* Add support for \t in printf
* Add ScalaDoc to RegNext

Add vector extension to OMISA

See https://github.com/riscv/riscv-v-spec/pull/351

Custommessage

* bump FIRRTL for async reset register fixes

* Bump firrtl to get verilog lint clean fix

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>

I$ accesses can be speculative, and raising the halt signal based
upon speculative accesses is problematic.

These errors can still be dealt with using a BusErrorUnit.