Bump the formal subdirectory to chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Add TLResourceRemover

* RegionReplicator: only check prefix when relevant

* Support incoherent access to AXI4 extmem through sbus

RoccBlackBox fixes for: 1) incorrect signal assigned to rocc_resp_bits_rd; 2) incorrect behavior in synthesis result (tested on FPGA) (#3035)

Removed TraceGen in HeterogeneousTileExampleConfig

Convert toaxe.py to Python3

Co-authored-by: Jiuyang liu <liujiuyang1994@gmail.com>

Partially reverts #2836, but in such a way that it works with the new QMC.

* Use new Chisel Decoder API

* CSR: fix decode when using new Chisel API

When using new API, io.rw.addr << 20 would not match any entry in
decode_table.

e.g. When io.rw.addr[11:0] == "h102", after left shift 20 it would
become "h10200000", which wont match SRET ("h10200073") as defined
in Instructions.scala. Note, SRET is not defined with DontCare.

Magically, old API can work with this case, which should not.

In this fix the least significant 20 bits of decode_table keys
are dropped to match addr.

* Make Decode logic width-safe

This involves ensuring all BitPats that correspond to a particular
portion of the decoded result are of the same width. BitPats with no
"don't cares" can be zero padded to the common width. BitPats with "don't
cares" that are too small are an error.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Zenithal <i@zenithal.me>

hardcode reg_vsstatus.xs to zero/dirty

* Fix typo: priviledged -> privileged

This incurs a small breaking change, but can be easily fixed.

* Add comments to amba and tilelink modules and fix typos.

Bind Verilog path with EICG_wrapper

Update Instructions with riscv-opcodes 

configs: add WithHypervisor config

[AXISBundleBits] re-add clonetype override