Explicitly use python3 for mem gen scripts

Co-authored-by: phthinh <hung3@e.ntu.edu.sg>
Co-authored-by: Yangyu Chen <cyy@cyyself.name>
Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

Bump verilator and rocket-tools

Related to https://github.com/chipsalliance/rocket-chip/issues/3228

* Bump verilator to 4.226; However, as spike recently needs
c++17, and verilator selects the c++ version based on Linux
distribution, we have to manually set it by CFG_CXXFLAGS_STD_NEWEST

* Bump rocket-tools to latest; This introduce the c++17 spike.

Ref to https://github.com/chipsalliance/rocket-chip/pull/3193

Populate tval with pc when ebreak

Generate correct lazyscope name

This reverts commit 69d260fa.

s1_req is not TLBReq and should be manually connected

Fixes https://github.com/chipsalliance/rocket-chip/issues/3165

+ replace .getPorts with DataMirror.modulePorts;

mill: enable zicntr test for TinyConfig

See https://github.com/chipsalliance/rocket-chip/pull/3202

Add other riscv-tests tests

Without PRINTF_CONF, it is always verbose

* nix: introduce toolchains for emulator and tests

* Add new CI on riscv-tests based on mill

+ Remove parenthesized forms of asUInt(), asSInt(), orR(), andR(), zext();

Ref to https://github.com/riscv/riscv-isa-manual/commit/51522f98b5cae989c7d161e00b20a08483a2301e
and https://github.com/riscv-software-src/riscv-isa-sim/commit/be5af59bcaca4dc90a0d276e1eccc4f4896b0373

There are two code paths for the spec "When a breakpoint ..,
occurs, mtval is written with the faulting virtual address".
One is hardware braekpoint, which is covered by
wb_reg_cause.isOneOf(Causes.breakpoint;
the other is software breakpoint, which is only
handled in CSRFile since ebreak is only decoded there,
and the main pipeline (RocketCore.scala) does not raise exception,
(tval_valid is false.B because wb_expt is false.B)

So to properly set tval, Another level of Mux
is needed.

* refactor ROMGenerator to chisel3. (#3091)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Arbiters to chisel3 (#3092)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor ResetCatchAndSync to chisel3. (#3093)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor ReorderQueue to chisel3. (#3094)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor MuxLiteral to chisel3. (#3098)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Counters to chisel3 (#3101)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port CLINT.scala to Chisel 3 (#3107)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port util/HellaQueue.scala to Chisel3 (#3108)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/IDecode to chisel3 (#3119)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/Frontend to chisel3 (#3118)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port util/ECC.scala to Chisel 3 (#3132)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/CRC to chisel3 (#3129)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port tile/fpu to chisel3 (#3127)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Broadcaster to chisel3 (#3102)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Fix HellaQueue IO type and imcomplete connections (#3157)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/RocketCore to chisel3 (#3121)

* Port rocket/RocketCore to chisel3

* WireInit -> WireDefault

* Try to fix unconnected id_scie_decoder

* Drop all implicit conversions in RocketCore

* Update src/main/scala/rocket/RocketCore.scala

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/NBDCache to chisel3 (#3117)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/ScratchpadSlavePort to chisel3 (#3115)

* Port rocket/ScratchpadSlavePort to chisel3

* Fix missing cloneType in ScratchpadSlavePort

* Fix MuxLookup hardware types in ScratchpadSlavePort

* Fix partial connection in ScratchpadSlavePort
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/TLB to Chisel3 (#3114)

* Port rocket/TLB to chisel3

* Remove implicit conversions in TLB
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Co-authored-by: SingularityKChen <chency_singularity@163.com>
Co-authored-by: rvsv39 <90169450+rvsv39@users.noreply.github.com>
Co-authored-by: sinofp <sinofp@tuta.io>
Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com>
Co-authored-by: Sharzy <me@sharzy.in>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Chisel3 port

Recent fesvrs require c++17

Support LazyModule cloning