Rebasing lost commits in chisel3_port (#3197)

* refactor ROMGenerator to chisel3. (#3091)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Arbiters to chisel3 (#3092)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor ResetCatchAndSync to chisel3. (#3093)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor ReorderQueue to chisel3. (#3094)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor MuxLiteral to chisel3. (#3098)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Counters to chisel3 (#3101)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port CLINT.scala to Chisel 3 (#3107)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port util/HellaQueue.scala to Chisel3 (#3108)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/IDecode to chisel3 (#3119)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/Frontend to chisel3 (#3118)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port util/ECC.scala to Chisel 3 (#3132)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/CRC to chisel3 (#3129)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port tile/fpu to chisel3 (#3127)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Broadcaster to chisel3 (#3102)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Fix HellaQueue IO type and imcomplete connections (#3157)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/RocketCore to chisel3 (#3121)

* Port rocket/RocketCore to chisel3

* WireInit -> WireDefault

* Try to fix unconnected id_scie_decoder

* Drop all implicit conversions in RocketCore

* Update src/main/scala/rocket/RocketCore.scala

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/NBDCache to chisel3 (#3117)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/ScratchpadSlavePort to chisel3 (#3115)

* Port rocket/ScratchpadSlavePort to chisel3

* Fix missing cloneType in ScratchpadSlavePort

* Fix MuxLookup hardware types in ScratchpadSlavePort

* Fix partial connection in ScratchpadSlavePort
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/TLB to Chisel3 (#3114)

* Port rocket/TLB to chisel3

* Remove implicit conversions in TLB
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Co-authored-by: SingularityKChen <chency_singularity@163.com>
Co-authored-by: rvsv39 <90169450+rvsv39@users.noreply.github.com>
Co-authored-by: sinofp <sinofp@tuta.io>
Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com>
Co-authored-by: Sharzy <me@sharzy.in>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>