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chipsalliance
rocket-chip
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dontdeleteme-singlestep
61c2e8c0
·
Don't raise the single-step interrupt when in debug mode
·
May 14, 2018
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pr-1443
37633bc7
·
Guard against integer overflow on the DiplomaticSRAM size.
·
May 23, 2018
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remove_pow2clockdivider_warning
af9f443e
·
Get rid of sim-only warning in Pow2ClockDivider
·
May 23, 2018
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port-anno-rocket
10fa0b32
·
changed the port anno so it uses a list of names instead of a mem mapping
·
Jun 04, 2018
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SimJTAG_remove_vpi
7f8d6f4d
·
Remove unnesessary VPI dependency from SimJTAG
·
Jun 11, 2018
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periphery_clock_changes
eff98cc2
·
Revert "Sram annos1 (#1490)"
·
Jun 14, 2018
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stride-prefetch
c8c64124
·
More code cleanup. Add logic to check that prefetch address supports Hints....
·
Jun 14, 2018
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tile-interrupt-tweaks
c84bb66a
·
subsystem: clean up connectInterrupts
·
Jun 27, 2018
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1518-port-bugfix
6a6e9cff
·
ports: CanHaveSlaveTLPortModuleImp bug fix
·
Jun 29, 2018
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rocket-chip-oski
c2a67b98
·
Merge pull request #1545 from freechipsproject/crossing-cleanups
·
Jul 18, 2018
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sbus-arbitration
5be8ccbd
·
subsystem: make sbus arbitration configurable
·
Jul 30, 2018
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periphery-helpers-2
631001e9
·
tile: disable monitors in slave crossing
·
Aug 03, 2018
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plic-dts
0ab65ab0
·
plic: Change device tree compat string to "sifive,plic-1.0.0"
·
Aug 10, 2018
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fix-async-reset-reg-race
8e7ad591
·
Clock SimJTAG/TCK during initialization to reset design properly
·
Aug 14, 2018
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refine-async-reset-reg-init-modeling
2de2ed42
·
Model AsyncResetReg's init reset behavior as level-sensitive
·
Aug 16, 2018
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rocc_dip
88714d37
·
fixed whitespace issues, changed package from tile.fpucp to rocket.fpucp per...
·
Aug 16, 2018
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dcachedip
79330707
·
changed PTW's interface to take in a function that returns the number of ports...
·
Aug 17, 2018
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bundle-bridge-splice
f01b175c
·
bundlebridge: first cut of splice
·
Aug 21, 2018
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beu-fix-dontdeleteme
00d57ffd
·
bump riscv-tools for debug workaround
·
Aug 25, 2018
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register-router-redux
4d3ba3dc
·
registerrouter: remove unused type parameter
·
Sep 27, 2018
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