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github.com
chipsalliance
rocket-chip
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dev

043926a1 · Merge pull request #3648 from chipsalliance/tile_int_domain · Jun 13, 2024

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tile_int_domain

ce9a2ecd · Interrupts coming outwards from the Tile should cross into a toPlicDomain · Jun 12, 2024

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merged_tl_credited

df74ae8a · Add option to use MergedCreditedCrossing in HierarchicalElements · Jun 11, 2024

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empty_diplomacy

4ac1529d · Add deprecated accessors to diplomacy package components · Jun 06, 2024

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naming

0e7230f2 · Set jtag capture desiredNames · Jun 04, 2024

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cp_fpu

2453dd4e · Allow pipeline coprocessor accesses into FPU · May 17, 2024

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width-fix

ebe730b0 · Fix extraction-width warnings in TLWidthWidget.scala · Apr 25, 2024

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ptw_gf

1a7a96c3 · PTW: traverse check GPA bits higher than HGATP mode only if valid · Apr 23, 2024

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mhtinst

960c1471 · Hypervisor: drive mtinst/htinst · Apr 23, 2024

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ifv_fix

3bd61748 · Merge remote-tracking branch 'origin/dev' into ifv · Apr 19, 2024

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abejgonzalez-patch-1

30fd302b · Use SV48 when possible · Apr 12, 2024

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tile-int-fix

c37e6300 · Fix tile interrupt sources · Apr 03, 2024

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plic-order

93fe30e8 · Fix connection order of meip/seip to plic · Apr 02, 2024

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sync

01303e74 · Merge remote-tracking branch 'origin/master' into sync · Mar 20, 2024

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ifv-old

73ee1960 · Update LazyRoCC blackbox · Mar 20, 2024

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master default protected

dbcb06af · PTW Hypervisor bug fixes: check GPA bits higher than HGATP.Mode (#3591) · Mar 20, 2024

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fix_s1_data

32b2d129 · Fix s1_data when coreDataBits > xLen · Mar 20, 2024

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tlfrag-assert

b036fa21 · Fix TLFragmenter assert · Mar 19, 2024

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hyp_ptw_gf

e5917a29 · remove pte_cache_addr, just use pte_addr · Mar 16, 2024

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precise_tlb_perms

bf6e57d8 · Support managers with < pageSize alignment · Mar 14, 2024

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