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chipsalliance
rocket-chip
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safe-bsb
6b59c2c3
·
coreplex: move buffers inside the coreplex
·
Mar 24, 2017
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verilator_flag
6daa9d89
·
Added --trace-underscore to make verilator generated waveform more useful
·
Mar 30, 2017
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dram-midas
1b197083
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java counters
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Mar 31, 2017
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hurricane
aec20532
·
bump tools for vcjal fix and vsetcfg macro
·
Apr 06, 2017
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hwacha-compat
e610a19e
·
use crossbar instead of bus for L1-L2 interconnect
·
Apr 13, 2017
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scottj/torture-itim
5cc068eb
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Merge remote-tracking branch 'origin/fix-itim' into scottj/torture-itim
·
May 04, 2017
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hwacha
d002f690
·
Bump hwacha for memory ordering fix
·
Jul 13, 2017
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update-readme-configs
a110d17e
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Update readme to reflect config name changes
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Jul 17, 2017
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test-fq
dd7c8910
·
tile: add flow queues on master d and slave a
·
Jul 29, 2017
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boom-thesis
577b9062
·
delete unnecessary instrumentation
·
Jul 30, 2017
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test-fq2
e5889ff5
·
Mitigate I$->D$->I$ critical path
·
Jul 31, 2017
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fix-ecc-waw
d54dca43
·
Don't merge stores that manifest WAW hazards
·
Aug 08, 2017
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maskrom-fsbl-build
87aafbae
·
Fix some scala lint
·
Aug 14, 2017
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boundary-fifo
08a5132a
·
coreplex: try moving the tile's FifoFixer inside the the tile
·
Aug 29, 2017
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chisel3_deprepkg
1a1cbde1
·
Move addSbtPlugin sbt-chisel-dep to its own file and add explicit sonatype...
·
Aug 30, 2017
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Scala212-almostcompatible
7006e028
·
Use Scala212-compatible versions of chisel3 and firrtl; bump compiler to...
·
Sep 12, 2017
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boom
21cce2cd
·
[boom] bump with bug fixes.
·
Sep 13, 2017
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boom-v1
0904e693
·
get rid of side effect of assertion synthesis
·
Sep 25, 2017
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fpga_pipeline_fpu
9c691449
·
FPU : simplify pipeline register generation in FMA
·
Sep 29, 2017
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store-buffer-fix
c07b25c7
·
Merge pull request #1021 from freechipsproject/fpga_pipeline_fpu
·
Oct 05, 2017
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