sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-31	Update bitfield syntax	Alasdair	1	-2/+2
2023-09-12	Remove effects	Tim Hutt	1	-4/+4
2023-08-01	Rename EXTZ and EXTS	Alasdair	1	-1/+1
2023-05-29	apply_headers: regenerate copyright headersupdate-copyright-headers	Philipp Tomsich	1	-1/+3
2021-07-29	Use headache to apply copyright header at request of Peter Sewell.	Robert Norton	1	-0/+68
2021-03-16	Initial implementation of new RVFI_DII socket format	Alex Richardson	1	-2/+3
2021-02-11	Remove unused register files.	Prashanth Mundkur	1	-2/+0
2019-08-19	RISC-V spec, without implicit casts	Alasdair Armstrong	1	-1/+7
2019-07-09	Add some missed logging guards.	Prashanth Mundkur	1	-2/+2
2019-07-01	Merge remote-tracking branch 'origin/master' into master-cleanup	Robert Norton	1	-1/+3
2019-06-28	Avoid implicit casts to string	Alasdair	1	-1/+3
2019-06-27	Zero extend rather than sign extend rvfi-dii reports (usefull for 32 rvfi-dii...	Alexandre Joannou	1	-1/+1
2019-06-27	Predicate more tracing with get_config_print_xxx.	Robert Norton	1	-1/+2
2019-05-10	Rename regbits to regidx, to clarify the type is an index and not the content...	Prashanth Mundkur	1	-1/+1
2019-05-03	Minor formatting cleanup and remove obsolete comments.	Prashanth Mundkur	1	-3/+0
2019-05-03	Fix compile due to missed effect declaration.	Prashanth Mundkur	1	-1/+1
2019-05-03	Don't assume regtype is bitvector in init_base_regs.	Robert Norton	1	-31/+31
2019-05-03	Fix a couple of warnings.	Robert Norton	1	-2/+4
2019-05-02	rvfi: fixes for RV32	Prashanth Mundkur	1	-1/+1
2019-05-02	rvfi: initialize registers between test runs.	Prashanth Mundkur	1	-0/+35
2019-04-24	Add extended model from cheri-merge.	Prashanth Mundkur	1	-0/+232