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author | Robert Norton <rmn30@cam.ac.uk> | 2019-05-03 14:44:03 +0100 |
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committer | Robert Norton <rmn30@cam.ac.uk> | 2019-05-03 14:44:03 +0100 |
commit | 32bcc0eca223fc0e2e25bc00caad8e11ee41f01a (patch) | |
tree | ed698a6c21b8680a7520f948444559d853f24be3 /model/riscv_regs.sail | |
parent | 7e15cdb8723b7aeb90bf86c5d50dce4b55c7ec66 (diff) | |
download | sail-riscv-32bcc0eca223fc0e2e25bc00caad8e11ee41f01a.zip sail-riscv-32bcc0eca223fc0e2e25bc00caad8e11ee41f01a.tar.gz sail-riscv-32bcc0eca223fc0e2e25bc00caad8e11ee41f01a.tar.bz2 |
Don't assume regtype is bitvector in init_base_regs.
Diffstat (limited to 'model/riscv_regs.sail')
-rw-r--r-- | model/riscv_regs.sail | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail index a085275..5fe771b 100644 --- a/model/riscv_regs.sail +++ b/model/riscv_regs.sail @@ -235,35 +235,35 @@ mapping creg_name : bits(3) <-> string = { val init_base_regs : unit -> unit effect {wreg} function init_base_regs () = { - x1 = EXTZ(0b0); - x2 = EXTZ(0b0); - x3 = EXTZ(0b0); - x4 = EXTZ(0b0); - x5 = EXTZ(0b0); - x6 = EXTZ(0b0); - x7 = EXTZ(0b0); - x8 = EXTZ(0b0); - x9 = EXTZ(0b0); - x10 = EXTZ(0b0); - x11 = EXTZ(0b0); - x12 = EXTZ(0b0); - x13 = EXTZ(0b0); - x14 = EXTZ(0b0); - x15 = EXTZ(0b0); - x16 = EXTZ(0b0); - x17 = EXTZ(0b0); - x18 = EXTZ(0b0); - x19 = EXTZ(0b0); - x20 = EXTZ(0b0); - x21 = EXTZ(0b0); - x22 = EXTZ(0b0); - x23 = EXTZ(0b0); - x24 = EXTZ(0b0); - x25 = EXTZ(0b0); - x26 = EXTZ(0b0); - x27 = EXTZ(0b0); - x28 = EXTZ(0b0); - x29 = EXTZ(0b0); - x30 = EXTZ(0b0); - x31 = EXTZ(0b0) + x1 = zero_reg; + x2 = zero_reg; + x3 = zero_reg; + x4 = zero_reg; + x5 = zero_reg; + x6 = zero_reg; + x7 = zero_reg; + x8 = zero_reg; + x9 = zero_reg; + x10 = zero_reg; + x11 = zero_reg; + x12 = zero_reg; + x13 = zero_reg; + x14 = zero_reg; + x15 = zero_reg; + x16 = zero_reg; + x17 = zero_reg; + x18 = zero_reg; + x19 = zero_reg; + x20 = zero_reg; + x21 = zero_reg; + x22 = zero_reg; + x23 = zero_reg; + x24 = zero_reg; + x25 = zero_reg; + x26 = zero_reg; + x27 = zero_reg; + x28 = zero_reg; + x29 = zero_reg; + x30 = zero_reg; + x31 = zero_reg } |