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path: root/model/riscv_insts_base.sail
AgeCommit message (Expand)AuthorFilesLines
2019-07-18Revert "Support DMB/DSB domains"Alasdair Armstrong1-11/+11
2019-07-18Support DMB/DSB domainsShaked Flur1-11/+11
2019-06-24Add PMP checks to physical memory accesses.Prashanth Mundkur1-9/+9
2019-06-24Narrow the external interface to riscv_mem to mem_{read,write,write_ea}.Prashanth Mundkur1-4/+4
2019-05-23Be more careful about matching only instructions that are defined for xlen be...Robert Norton1-5/+6
2019-05-10Rename regbits to regidx, to clarify the type is an index and not the content...Prashanth Mundkur1-15/+15
2019-05-10Use an explicit enum to indicate the retire status as opposed to a boolean to...Prashanth Mundkur1-42/+42
2019-05-10Print canonical assembly for immediate loads/storesJames Clarke1-3/+3
2019-05-03Minor formatting cleanup and remove obsolete comments.Prashanth Mundkur1-2/+0
2019-05-03Fix inconsistency in accessing PC/nextPC, which also clarifies which handlers...Prashanth Mundkur1-4/+4
2019-05-02Push address calculation inside the data_check_addr hook and rename it to dat...rmn30Robert Norton1-6/+8
2019-05-01Add base address register as extra argument to ext_data_check_addr hook to as...Robert Norton1-2/+2
2019-04-24Add extended model from cheri-merge.Prashanth Mundkur1-58/+88
2019-03-14Merge branch 'master' into rmem_interpreterJon French1-49/+103
2019-03-12refactor memory access to use new sail intrinsicsJon French1-11/+11
2019-03-12fix missing separator in shift instruction disassembliesJon French1-2/+2
2019-03-11Add tlbs for Sv32 and Sv48, and some fixes to sfence.vma.Prashanth Mundkur1-18/+10
2019-03-11Fixes for Sv39 TLB.Prashanth Mundkur1-5/+10
2019-03-04Minor edit for consistency.Prashanth Mundkur1-5/+5
2019-03-04Fix missed RV32 check for shamt in sll/srl.Prashanth Mundkur1-5/+13
2019-02-19Use sizeof xlen instead of the value definitions of xlen.Prashanth Mundkur1-39/+39
2019-02-15Add xlen guards on double-word operations to make them RV64-only.Prashanth Mundkur1-12/+12
2019-02-14Handle shamt being 5 bits in RV32 instead of 6; also fix a missed case of dis...Prashanth Mundkur1-8/+14
2019-02-11Fix xlen variable name.Prashanth Mundkur1-32/+32
2019-02-11Handle SXL/UXL not being present in mstatus in RV32 by using explicit getters...Prashanth Mundkur1-1/+1
2019-02-08Add xlen guards on encdec and assembly guards, and encdec for c.jal.Prashanth Mundkur1-11/+54
2019-01-29Add more of the 'N' standard extension.Prashanth Mundkur1-1/+3
2019-01-25SRET should be illegal if S-mode is not supported.Prashanth Mundkur1-1/+1
2019-01-25Factor out each extension into separate files, do some minor cleanup.Prashanth Mundkur1-0/+667
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