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| author | Jon French <jf451@cam.ac.uk> | 2019-03-12 11:13:45 +0000 |
|---|---|---|
| committer | Jon French <jf451@cam.ac.uk> | 2019-03-12 11:13:45 +0000 |
| commit | eab254dedc3f72d5ab1b6bbcae69cfebf15988dc (patch) | |
| tree | be849318d3bb29e128f36394959529f5237ffc24 /model/riscv_insts_base.sail | |
| parent | e50126070b01e7494fc4d1348b96d2af30f7c8ae (diff) | |
| download | sail-riscv-eab254dedc3f72d5ab1b6bbcae69cfebf15988dc.zip sail-riscv-eab254dedc3f72d5ab1b6bbcae69cfebf15988dc.tar.gz sail-riscv-eab254dedc3f72d5ab1b6bbcae69cfebf15988dc.tar.bz2 | |
fix missing separator in shift instruction disassemblies
Diffstat (limited to 'model/riscv_insts_base.sail')
| -rw-r--r-- | model/riscv_insts_base.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index 8a9af81..d18f92f 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -201,7 +201,7 @@ mapping shiftiop_mnemonic : sop <-> string = { } mapping clause assembly = SHIFTIOP(shamt, rs1, rd, op) - <-> shiftiop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ hex_bits_6(shamt) + <-> shiftiop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_6(shamt) /* ****************************************************************** */ union clause ast = RTYPE : (regbits, regbits, regbits, rop) @@ -470,7 +470,7 @@ mapping shiftiwop_mnemonic : sopw <-> string = { } mapping clause assembly = SHIFTIWOP(shamt, rs1, rd, op) - <-> shiftiwop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ hex_bits_5(shamt) + <-> shiftiwop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt) /* ****************************************************************** */ union clause ast = FENCE : (bits(4), bits(4)) |