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riscv_insts_base.sail
Age
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Author
Files
Lines
2019-03-12
fix missing separator in shift instruction disassemblies
Jon French
1
-2
/
+2
2019-03-11
Add tlbs for Sv32 and Sv48, and some fixes to sfence.vma.
Prashanth Mundkur
1
-18
/
+10
2019-03-11
Fixes for Sv39 TLB.
Prashanth Mundkur
1
-5
/
+10
2019-03-04
Minor edit for consistency.
Prashanth Mundkur
1
-5
/
+5
2019-03-04
Fix missed RV32 check for shamt in sll/srl.
Prashanth Mundkur
1
-5
/
+13
2019-02-19
Use sizeof xlen instead of the value definitions of xlen.
Prashanth Mundkur
1
-39
/
+39
2019-02-15
Add xlen guards on double-word operations to make them RV64-only.
Prashanth Mundkur
1
-12
/
+12
2019-02-14
Handle shamt being 5 bits in RV32 instead of 6; also fix a missed case of dis...
Prashanth Mundkur
1
-8
/
+14
2019-02-11
Fix xlen variable name.
Prashanth Mundkur
1
-32
/
+32
2019-02-11
Handle SXL/UXL not being present in mstatus in RV32 by using explicit getters...
Prashanth Mundkur
1
-1
/
+1
2019-02-08
Add xlen guards on encdec and assembly guards, and encdec for c.jal.
Prashanth Mundkur
1
-11
/
+54
2019-01-29
Add more of the 'N' standard extension.
Prashanth Mundkur
1
-1
/
+3
2019-01-25
SRET should be illegal if S-mode is not supported.
Prashanth Mundkur
1
-1
/
+1
2019-01-25
Factor out each extension into separate files, do some minor cleanup.
Prashanth Mundkur
1
-0
/
+667
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