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| author | Valentin Robert <valentin.robert.42@gmail.com> | 2025-12-08 06:03:00 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-12-08 14:03:00 +0000 |
| commit | 1993f2d414fe6326dc0855a901d620b82f582c71 (patch) | |
| tree | 6f10a57683f003767eb0ea4cddd4af72278c08a7 /model/sys/vmem_utils.sail | |
| parent | 1c7910bc1a23107a9c36297e4ff733e457e052a4 (diff) | |
| download | sail-riscv-master.zip sail-riscv-master.tar.gz sail-riscv-master.tar.bz2 | |
Scatter the termination module in such a way that one could require some
termination measures without having to include every single instruction
in the output. This makes building a subset of the model easier.
The termination measures for `vmem_read_addr` and `vmem_write_addr` no
longer need to be protected only for the Rocq output, so they get taken
out of the `$iftarget coq`.
Diffstat (limited to 'model/sys/vmem_utils.sail')
| -rw-r--r-- | model/sys/vmem_utils.sail | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/model/sys/vmem_utils.sail b/model/sys/vmem_utils.sail index c07b661..1b6216c 100644 --- a/model/sys/vmem_utils.sail +++ b/model/sys/vmem_utils.sail @@ -172,6 +172,9 @@ function vmem_read_addr(vaddr, offset, width, acc, aq, rl, res) = { Ok(data) } +// This lets the Rocq extraction know why the repeat loop above terminates +termination_measure vmem_read_addr repeat n + val vmem_write_addr : forall 'width, is_mem_width('width). (virtaddr, int('width), bits(8 * 'width), MemoryAccessType(ext_access_type), bool, bool, bool) -> result(bool, ExecutionResult) @@ -227,6 +230,9 @@ function vmem_write_addr(vaddr, width, data, acc, aq, rl, res) = { Ok(write_success) } +// This lets the Rocq extraction know why the repeat loop above terminates +termination_measure vmem_write_addr repeat n + val vmem_read : forall 'width, is_mem_width('width). (regidx, xlenbits, int('width), MemoryAccessType(ext_access_type), bool, bool, bool) -> result(bits(8 * 'width), ExecutionResult) |