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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2026-04-26 14:43:22 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-26 19:43:22 +0000 |
| commit | da838a7a6a06464caa1c61fe55b20b8e30d1aee1 (patch) | |
| tree | f449cf286fac56d8ae0a142c70b284eb64e5b9ec | |
| parent | 6884514c374b9237c95e94578e92d8c61ad11a6a (diff) | |
| download | sail-riscv-master.tar.gz sail-riscv-master.tar.bz2 sail-riscv-master.zip | |
Prepare release 0.11. (#1681)HEAD2026-04-27-da838a70.11master
Update release notes and increment version.
| -rw-r--r-- | cmake/project_version.cmake | 2 | ||||
| -rw-r--r-- | doc/ChangeLog.md | 16 |
2 files changed, 15 insertions, 3 deletions
diff --git a/cmake/project_version.cmake b/cmake/project_version.cmake index 984ec102..3b52c424 100644 --- a/cmake/project_version.cmake +++ b/cmake/project_version.cmake @@ -1,5 +1,5 @@ # Increment this appropriately at tag-and-release time. -set(sail_riscv_release_version "0.10") +set(sail_riscv_release_version "0.11") # Sets GIT_EXECUTABLE find_package(Git) diff --git a/doc/ChangeLog.md b/doc/ChangeLog.md index dba30751..f9dd3f56 100644 --- a/doc/ChangeLog.md +++ b/doc/ChangeLog.md @@ -1,10 +1,19 @@ # Release notes for the next version +# Release notes for version 0.11 + - Updates to the [configuration file](../config/config.json.in): - - PMAs now have an additional `atomic_support` attribute for the level - of atomicity supported in the memory region; see `memory.regions`. + - PMAs now have additional attributes (see `memory.regions`): + - `mem_type` for the type of memory covered by the region, + which can be either `MainMemory` or `IOMemory`. + - `atomic_support` for the level of atomicity supported in the + memory region. + - `supports_pte_read` and `supports_pte_write` for whether the region + supports the hardware read and write of page table entries respectively. - Writable bits of the `scounteren` CSR can now be specified; see `base.scounteren_writable_bits`. + - The behavior when reserved modes are written to the `mtvec` and + `stvec` CSRs can now be specified; see `base.reserved_behavior.xtvec_mode`. - The time limit that wait instructions (e.g. WFI, WRS.NTO, WRS.STO) can wait for is now configurable; see `platform.max_time_to_wait` (see also https://github.com/riscv/sail-riscv/issues/1564). The @@ -35,6 +44,9 @@ to `true` to match some implementations such as Spike. The earlier `platform.reservation_set_size_exp` parameter has moved to `platform.reservation.reservation_set_size_exp`. + - A new `platform.simple_interrupt_generator.base` parameter specifies + the memory location of the simple interrupt generator; see below for + more on this device. - The following extensions have been added: - Ziccamoa |