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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 14:09:30 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 14:09:30 -0800 |
| commit | 3f7de72df81894456d47b3cff63103847d010059 (patch) | |
| tree | 6edb4ec0deb6f07d11cb376475d07a17b0051052 | |
| parent | f2c27bcc36ba113a851b211956a6eb432ee658b5 (diff) | |
| download | sail-riscv-3f7de72df81894456d47b3cff63103847d010059.zip sail-riscv-3f7de72df81894456d47b3cff63103847d010059.tar.gz sail-riscv-3f7de72df81894456d47b3cff63103847d010059.tar.bz2 | |
Fix 64-bit constants.
| -rw-r--r-- | model/riscv_platform.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail index 57b7f69..25739fc 100644 --- a/model/riscv_platform.sail +++ b/model/riscv_platform.sail @@ -101,9 +101,9 @@ register mtimecmp : xlenbits // memory-mapped internal clint register. * bffc mtime hi */ -let MSIP_BASE : xlenbits = 0x0000000000000000 -let MTIMECMP_BASE : xlenbits = 0x0000000000004000 -let MTIME_BASE : xlenbits = 0x000000000000bff8 +let MSIP_BASE : xlenbits = EXTZ(0x00000) +let MTIMECMP_BASE : xlenbits = EXTZ(0x04000) +let MTIME_BASE : xlenbits = EXTZ(0x0bff8) val clint_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg} function clint_load(addr, width) = { |