From 3f7de72df81894456d47b3cff63103847d010059 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur <prashanth.mundkur@gmail.com>
Date: Mon, 11 Feb 2019 14:09:30 -0800
Subject: Fix 64-bit constants.

---
 model/riscv_platform.sail | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail
index 57b7f69..25739fc 100644
--- a/model/riscv_platform.sail
+++ b/model/riscv_platform.sail
@@ -101,9 +101,9 @@ register mtimecmp : xlenbits  // memory-mapped internal clint register.
  * bffc mtime hi
  */
 
-let MSIP_BASE     : xlenbits = 0x0000000000000000
-let MTIMECMP_BASE : xlenbits = 0x0000000000004000
-let MTIME_BASE    : xlenbits = 0x000000000000bff8
+let MSIP_BASE     : xlenbits = EXTZ(0x00000)
+let MTIMECMP_BASE : xlenbits = EXTZ(0x04000)
+let MTIME_BASE    : xlenbits = EXTZ(0x0bff8)
 
 val clint_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg}
 function clint_load(addr, width) = {
-- 
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