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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 13:20:16 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 13:20:16 -0800 |
| commit | f2c27bcc36ba113a851b211956a6eb432ee658b5 (patch) | |
| tree | 99ec29b924ec4e075a5855f92c6905814155a77c | |
| parent | 04431f38e310ff979aee6bd9b10966ffb11b5045 (diff) | |
| download | sail-riscv-f2c27bcc36ba113a851b211956a6eb432ee658b5.zip sail-riscv-f2c27bcc36ba113a851b211956a6eb432ee658b5.tar.gz sail-riscv-f2c27bcc36ba113a851b211956a6eb432ee658b5.tar.bz2 | |
Fix mvendorid width.
| -rw-r--r-- | model/riscv_insts_zicsr.sail | 2 | ||||
| -rw-r--r-- | model/riscv_sys_regs.sail | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index aac2266..7585565 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -17,7 +17,7 @@ function readCSR csr : csreg -> xlenbits = { let res : xlenbits = match csr { /* machine mode */ - 0xF11 => mvendorid, + 0xF11 => EXTZ(mvendorid), 0xF12 => marchid, 0xF13 => mimpid, 0xF14 => mhartid, diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index d659f5f..bf50dcb 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -353,7 +353,7 @@ function retire_instruction() -> unit = { } /* informational registers */ -register mvendorid : xlenbits // FIXME: this should be 32-bit +register mvendorid : bits(32) register mimpid : xlenbits register marchid : xlenbits /* TODO: this should be readonly, and always 0 for now */ |