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path: root/src/target/armv8_opcodes.h
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2024-02-15portability fix: Switch binary literals to hexSevan Janiyan1-67/+67
Allows build with legacy toolchains which do not support C23 nor GCC extension for binary literals. Change-Id: I742d3a8a86bf16f81421d11c59d3cb155ee17aed Signed-off-by: Sevan Janiyan <venture37@geeklan.co.uk> Reviewed-on: https://review.openocd.org/c/openocd/+/8123 Tested-by: jenkins Reviewed-by: Jörg Wunsch <openocd@uriah.heep.sax.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-09-17target/aarch64: add AArch64 mdd and mwd supportDaniel Goehring1-0/+4
For ARMv8, add AArch64 mdd and mwd support. AArch32 not supported. Change-Id: I25490471e16943e5a67d7649595d77643aa9a095 Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7192 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2022-09-13openocd: remove CamelCase symbols *xPSR*Antonio Borneo1-2/+2
We have left the camelcase symbols *xPSR* for some time, to avoid any conflict with possibly pending patches in gerrit. With the approaching v0.12.0-rc1, it's time to revisit it. The patches in gerrit that conflict with this rename are all not merge-able due to conflicts or due to negative review. Drop these CamelCase symbols. Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7155 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-07-23openocd: src: replace the incomplete GPL-2.0-or-later license tagAntonio Borneo1-12/+4
Few files have the FSF boilerplate without the latest statement on where to get the GPL license. Manually replace the FSF boilerplate with the SPDX tag. While there, reorganize the copyright statement. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I0c908d01c010e24f9c7e94885e7fbed4ecf26a86 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7063 Tested-by: jenkins
2021-07-20target/arm: opcodes: rename CamelCase symbols and uppercase variablesAntonio Borneo1-59/+59
No major cross dependencies, mostly changes internal to each file/function. Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6340 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Xiang W <wxjstz@126.com>
2020-03-12target/armv8_opcodes: use T32 instructions when the PE is in AArch32 stateTarek BOCHKATI1-0/+8
As stated in ARM v8-A Architecture Reference Manual (ARM DDI 0487E.a) in Chapter H4.3 DCC and ITR access modes: Writes to EDITR trigger the instruction to be executed if the PE is in Debug state: - If the PE is in AArch64 state, this is an A64 instruction. - If the PE is in AArch32 state, this is a T32 instruction But in armv8_opcodes specifically in t32_opcodes we were using some A32 instructions for HLT, LDRx and STRx opcodes. Using the correct LDRx and STRx opcodes, fixes 16 and 8 bits memory access when the PE is in AArch32 state. Change-Id: Ib1acbdd4966297e7b069569bcb8deea3c3993615 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5346 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12target/aarch64: fix soft breakpoint when PE is in AArch32 stateTarek BOCHKATI1-0/+1
Before this patch aarch64_set_breakpoint was using either A64, or A32 HLT opcode by relying on armv8_opcode helper. This behaviors ignores the fact that in AArch32 state the core could execute Thumb-2 instructions, and gdb could request to insert a soft bkpt in a Thumb-2 code chunk. In this change, we check the core_state and bkpt length to know the correct opcode to use. Note: based on https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html if bkpt length/kind == 3, we should replace a 32-bit Thumb-2 opcode, then we use twice the 16 bits Thumb-2 bkpt opcode and we fix-up the length to 4 bytes, in order to set correctly the bpkt. Change-Id: I8f3551124412c61d155eae87761767e9937f917d Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5355 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-03-10Support AArch64 SIMD/FP registers read/writeOmair Javaid1-0/+8
This patch adds support in openOCD to read/write AArch64 SIMD/FP registers. This patch depends on a previous patch which adds support to generation of target xml by openOCD with nested architecture defined types. AArch64 SIMD/FP registers assumes various types and to support all types we implement them as architecture defined type aarch64v which in turn consists of various architecture defined types. This is compatible with AArch64-FPU target xml in GDB. Please refer to binutils-gdb/gdb/features/aarch64-fpu.xml Change-Id: I7ffb0c21b3c2e08f13720b765408b30aab2a9808 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4373 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-04target aarch64: rework memory read/write to use 8/16/32 bit operationsBas Vermeulen1-0/+14
The existing code only used Memory Access mode to read memory, which uses 32 bit operations only. Rework the code to check the alignment/size of the read/write operation, and use the Memory Access mode to read aligned 32 bit memory. When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW} instead. The exception handling is still the same as it was before (meaning it breaks when things go wrong), but I can now read an 8 bit register correctly. Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15 Signed-off-by: Bas Vermeulen <bas@daedalean.ai> Reviewed-on: http://openocd.zylin.com/4301 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: refactor SCTLR manipulationMatthias Welwarsky1-0/+4
Reduce SLOCs in SCTLR retrieval and modification functions and make them less complex. Change-Id: Ida1a99c223743247f171b52eef80dc9886802101 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3982 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: fix software breakpoints when in aarch32 stateMatthias Welwarsky1-0/+5
Use the correct opcode for Aarch32 state, both for the breakpoint instruction itself and the cache handling functions. Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3981 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-10aarch64: remove "mrs <Xt>, currentel" opcodeMatthias Welwarsky1-5/+0
"currentel" special register is not accessible in debug state. Change-Id: I9022b01b423cd9ae8227ed018d6166078ba44832 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: discard async aborts on entering debug stateMatthias Welwarsky1-0/+3
recommended for Corte-A8 cores, not sure if necessary for ARMv8 based cores as well. Change-Id: Ibcb36170c5fac6a6b132de17f734c70a56919f9b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: cache identification for aarch32 stateMatthias Welwarsky1-0/+1
Use proper T32 opcodes for cache identification when the PE is in Aarch32 state Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix mode switchingMatthias Welwarsky1-3/+9
DCPS only allows to enter higher ELs, for lower ELs you need to use DRPS. Also, of course the encoding differs between A64 and T32. Both DCPS and DRPS also clobber DLR and DSPSR, which then need to be restored on resume. Change-Id: Ifa3dcfa94212702e57170bd59fd0bb25495fb6fd Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: register access rewriteMatthias Welwarsky1-4/+13
All register access is now performed through common read/write functions, which delegate the actual register access to the armv8_common object. armv8_common contains function pointers to direct read and write requests to the respective low-level functions for each PE state. The respective read/write functions are selected on debug state entry. At the same time, T32 opcodes are now formatted for ITR in dpmv8_exec_opcode() and the T32_FMTITR macro is removed from global visibility. Change-Id: I9eaef017c7cc9e0c531e693c534901bfdbdb842c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: provide virt2phys commandMatthias Welwarsky1-0/+7
Use AT commands to translate virtual to physical addresses based on current MMU configuration. Change-Id: I1bbd7d674c435541b617b17022fa9f7f0f01bdab Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: armv8 cache functions updateMatthias Welwarsky1-0/+1
Update cache identification to match functionality present in armv7a_cache.c Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add basic Aarch32 supportMatthias Welwarsky1-4/+31
Add database for common, equivalent opcodes for Aarch32 and Aarch64 execution states Revisit all functions that access Aarch64 specific registers or use Aarch64 opcodes and rewrite them to act depending on current state of the core. Add core register access functions for Aarch32 state Add function to determine the core execution state without reading DSPSR. Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add cache handling functionsMatthias Welwarsky1-0/+2
For now only D-Cache flush (Clean&Invalidate) and I-Cache invalidate are implemented. That's enough for software breakpoints. Change-Id: I8e96d645a230b51e3490403f4564e59ba6a76cf3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use correct instruction for software breakpointsMatthias Welwarsky1-0/+3
External debuggers need to use HLT, not BRK. HLT generates a halting debug event while BRK generates a debug exception for self-hosted debugging. Change-Id: I24024b83668107f73a14cc75d951134917269e5c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add symbolic definitions for armv8 opcodesMatthias Welwarsky1-0/+126
To replace hexadecimal constants with descriptive names and increase flexibility. Change-Id: I6f7b6f045866ed8b9360f54b640ecdb307eebc51 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
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