diff options
| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-10-26 17:32:43 +0200 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2017-02-24 09:11:52 +0000 |
| commit | 5d00fd9d1dc504335dd71e474a3d61dec7696c40 (patch) | |
| tree | cd5f3092f02a8599de8bbd3d7265e4f939f0a5f6 /src/target/armv8_opcodes.h | |
| parent | 7c85165bc1a606883faa9bec51ebefbc652301f4 (diff) | |
| download | riscv-openocd-5d00fd9d1dc504335dd71e474a3d61dec7696c40.zip riscv-openocd-5d00fd9d1dc504335dd71e474a3d61dec7696c40.tar.gz riscv-openocd-5d00fd9d1dc504335dd71e474a3d61dec7696c40.tar.bz2 | |
aarch64: fix software breakpoints when in aarch32 state
Use the correct opcode for Aarch32 state, both for the breakpoint
instruction itself and the cache handling functions.
Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3981
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'src/target/armv8_opcodes.h')
| -rw-r--r-- | src/target/armv8_opcodes.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h index 53dcb7e..94694bc 100644 --- a/src/target/armv8_opcodes.h +++ b/src/target/armv8_opcodes.h @@ -148,6 +148,7 @@ #define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5)) #define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5)) +#define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF)) #define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt)) #define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F)) @@ -171,6 +172,10 @@ enum armv8_opcode { ARMV8_OPC_DCPS, ARMV8_OPC_DRPS, ARMV8_OPC_ISB_SY, + ARMV8_OPC_DCCISW, + ARMV8_OPC_DCCIVAC, + ARMV8_OPC_ICIVAU, + ARMV8_OPC_HLT, ARMV8_OPC_NUM, }; |