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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-10-20 13:20:26 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-10 14:18:34 +0100 |
| commit | 62c2eb4b284e0a3deb2aad7163354200bd93e634 (patch) | |
| tree | 8dce6921caaeb3843015c845f6e03ec05ef14b0f /src/target/armv8_opcodes.h | |
| parent | 946958cb723f0b123505234275ce9a653ddbfbd2 (diff) | |
| download | riscv-openocd-62c2eb4b284e0a3deb2aad7163354200bd93e634.zip riscv-openocd-62c2eb4b284e0a3deb2aad7163354200bd93e634.tar.gz riscv-openocd-62c2eb4b284e0a3deb2aad7163354200bd93e634.tar.bz2 | |
aarch64: cache identification for aarch32 state
Use proper T32 opcodes for cache identification when the PE is in
Aarch32 state
Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Diffstat (limited to 'src/target/armv8_opcodes.h')
| -rw-r--r-- | src/target/armv8_opcodes.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h index e57e7e9..b489d57 100644 --- a/src/target/armv8_opcodes.h +++ b/src/target/armv8_opcodes.h @@ -160,6 +160,7 @@ #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt) enum armv8_opcode { + READ_REG_CTR, READ_REG_CLIDR, READ_REG_CSSELR, READ_REG_CCSIDR, |