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riscv-openocd.git
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armv8_opcodes.h
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Author
Files
Lines
2021-07-20
target/arm: opcodes: rename CamelCase symbols and uppercase variables
Antonio Borneo
1
-59
/
+59
2020-03-12
target/armv8_opcodes: use T32 instructions when the PE is in AArch32 state
Tarek BOCHKATI
1
-0
/
+8
2020-03-12
target/aarch64: fix soft breakpoint when PE is in AArch32 state
Tarek BOCHKATI
1
-0
/
+1
2018-03-10
Support AArch64 SIMD/FP registers read/write
Omair Javaid
1
-0
/
+8
2018-01-04
target aarch64: rework memory read/write to use 8/16/32 bit operations
Bas Vermeulen
1
-0
/
+14
2017-02-24
aarch64: refactor SCTLR manipulation
Matthias Welwarsky
1
-0
/
+4
2017-02-24
aarch64: fix software breakpoints when in aarch32 state
Matthias Welwarsky
1
-0
/
+5
2017-02-10
aarch64: remove "mrs <Xt>, currentel" opcode
Matthias Welwarsky
1
-5
/
+0
2017-02-10
aarch64: discard async aborts on entering debug state
Matthias Welwarsky
1
-0
/
+3
2017-02-10
aarch64: cache identification for aarch32 state
Matthias Welwarsky
1
-0
/
+1
2017-02-10
aarch64: fix mode switching
Matthias Welwarsky
1
-3
/
+9
2017-02-10
aarch64: register access rewrite
Matthias Welwarsky
1
-4
/
+13
2017-02-10
aarch64: provide virt2phys command
Matthias Welwarsky
1
-0
/
+7
2017-02-10
aarch64: armv8 cache functions update
Matthias Welwarsky
1
-0
/
+1
2017-02-10
aarch64: add basic Aarch32 support
Matthias Welwarsky
1
-4
/
+31
2017-02-10
aarch64: add cache handling functions
Matthias Welwarsky
1
-0
/
+2
2017-02-10
aarch64: use correct instruction for software breakpoints
Matthias Welwarsky
1
-0
/
+3
2017-02-10
aarch64: add symbolic definitions for armv8 opcodes
Matthias Welwarsky
1
-0
/
+126