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2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
2021-07-20target/arm: rename CamelCase symbolsAntonio Borneo1-1/+1
No major cross dependencies, mostly changes internal to each file/function. Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6338 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Xiang W <wxjstz@126.com>
2021-05-22target/arm_dpm: rename 'wp_pc' as 'wp_addr'Antonio Borneo1-2/+6
The field 'wp_pc' was originally introduced in commit 55eeea7fceb6 ("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009 to contain the address of the instruction which triggered a watchpoint. Later on with commit 651b861d5d5f ("target/aarch64: Add watchpoint support") it has been reused in to hold directly the memory address that triggered a watchpoint. Rename 'wp_pc' as 'wp_addr' and change its doxygen description. While there, fix the format string to print the field. Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6204 Tested-by: jenkins Reviewed-by: Liming Sun <limings@nvidia.com>
2020-07-08coding style: add arguments to function prototypesAntonio Borneo1-16/+16
Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types FUNCTION_ARGUMENTS -f {} \; This patch also fixes an incorrect function prototype in zy1000.c. ZY1000 minidriver implementation overrides the function arm11_run_instr_data_to_core_noack_inner(), but the prototype is not the same as in src/target/arm11_dbgtap.c and to avoid compile error it was changed also the prototype of the called function arm11_run_instr_data_to_core_noack_inner_default(). Change-Id: I476cda8cdb0e1e280795b3b43ca95c40d09e4a3d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5630 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-11-06target/cortex_a: remove duplicate code to read target registersAntonio Borneo1-0/+1
The functions cortex_a_dap_{read,write}_coreregister_u32() are duplicate of the functions dpm_{read,write}_reg(). Remove both duplicated functions in cortex_a.c while export only dpm_read_reg(), since dpm_write_reg() is currently not used. Rename dpm_read_reg() as arm_dpm_read_reg() to keep uniform the naming style. Change-Id: I501bc99dc402039e630c47917a086a0bb382782c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4747 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2018-11-06target/arm_dpm: uniform names of exported functionsAntonio Borneo1-1/+1
The name of the function dpm_modeswitch() does not follow the common style of the other function names in the same file. Rename it as arm_dpm_modeswitch(). Change-Id: Idebf3c7bbddcd9b3c7b44f8d0dea1e5f7549b0eb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4756 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2017-02-10aarch64: register access rewriteMatthias Welwarsky1-2/+3
All register access is now performed through common read/write functions, which delegate the actual register access to the armv8_common object. armv8_common contains function pointers to direct read and write requests to the respective low-level functions for each PE state. The respective read/write functions are selected on debug state entry. At the same time, T32 opcodes are now formatted for ITR in dpmv8_exec_opcode() and the T32_FMTITR macro is removed from global visibility. Change-Id: I9eaef017c7cc9e0c531e693c534901bfdbdb842c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: unify armv7-a and armv8 debug entry decodingMatthias Welwarsky1-12/+12
Make DSCR_RUN_MODE() usable for armv8 and arm7 debug Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix entry into debug stateMatthias Welwarsky1-1/+1
- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this bit are ignored but we should not do them anyway - use dpmv8 function to report the reason for debug entry - WFAR is a 64bit register Change-Id: I07b81ecf105ceb7c3ae2f764bb408eb973c1d1de Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: introduce dpm extension for ARMv8Matthias Welwarsky1-1/+4
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add ARMv8 AARCH64 support filesDavid Ung1-0/+7
Add new AARCH64 target and ARMv8 support files. This is an instantiation from the cortex_a files but modified to support 64bit ARMv8. Not all features are complete, notably breakpts and single stepping are not yet implemented. Currently it lets you halt of the processors, resume, dump cpu registers, read/write memory and getting a stack trace with gdb. > halt invalid mode value encountered 5 target state: halted unrecognized psr mode: 0x5 target halted in ARM state due to debug-request, current mode: UNRECOGNIZED cpsr: 0x600001c5 pc: 0x00093528 MMU: disabled, D-Cache: disabled, I-Cache: disabled > targets TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* cpu0 aarch64 little cpu.dap halted > reg ===== arm v8 registers (0) r0 (/64): 0x00000000FFFFFFED (dirty) (1) r1 (/64): 0x00000000F76E4000 (2) r2 (/64): 0x0000000000000000 (3) r3 (/64): 0x0000000000010000 (4) r4 (/64): 0xFFFFFFC06E2939E1 (5) r5 (/64): 0x0000000000000018 (6) r6 (/64): 0x003A699CFB3C8480 (7) r7 (/64): 0x0000000053555555 (8) r8 (/64): 0x00FFFFFFFFFFFFFF (9) r9 (/64): 0x000000001FFEF992 (10) r10 (/64): 0x0000000000000001 (11) r11 (/64): 0x0000000000000000 (12) r12 (/64): 0x00000000000000F0 (13) r13 (/64): 0x00000000EFDFEAC8 (14) r14 (/64): 0x00000000F6DDA659 (15) r15 (/64): 0x0000000000000000 (16) r16 (/64): 0xFFFFFFC0000F9094 (17) r17 (/64): 0x0000000000000000 (18) r18 (/64): 0x0000000000000000 (19) r19 (/64): 0xFFFFFFC00087C000 (20) r20 (/64): 0x0000000000000002 (21) r21 (/64): 0xFFFFFFC000867C28 (22) r22 (/64): 0xFFFFFFC000916A52 (23) r23 (/64): 0xFFFFFFC00116D8B0 (24) r24 (/64): 0xFFFFFFC000774A0C (25) r25 (/64): 0x000000008007B000 (26) r26 (/64): 0x000000008007D000 (27) r27 (/64): 0xFFFFFFC000080450 (28) r28 (/64): 0x0000004080000000 (29) r29 (/64): 0xFFFFFFC00087FF20 (30) r30 (/64): 0xFFFFFFC000085114 (31) sp (/64): 0xFFFFFFC00087FF20 (32) pc (/64): 0xFFFFFFC000093528 (33) xPSR (/64): 0x00000000600001C5 And from gdb (gdb) bt #0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87 #1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107 #2 0x0000000000000000 in ?? () Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add 64bit register handling.David Ung1-0/+10
Add various function to read/write ARMv8 registers. Change-Id: I16f2829bdd0e87b050a51e414ff675d5c21bcbae Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-12-08cortex_a: remove partnum magic from arp_examine and dbginitMatthias Welwarsky1-0/+21
Depending on the Debug implementation the "OS Lock" feature might be implemented or not. It is not actually depending on the part number of the implemented ARM core but on the DBGOSLSR.OSLM bits. This patch removes querying the part number and implements proper parsing of OSLM. Result is a more generic approach that will work out-of-box on more devices. Change-Id: I79e052869c2f9af1d7fdedef42faddb7292e7332 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3213 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-05-24Make #include guard naming consistentMarc Schink1-3/+3
Change-Id: Ie13e8af0bb74ed290f811dcad64ad06c9d8cb4fa Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2956 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-03-15cortex_a : optimize apb read/write access.Evan Hunter1-13/+50
Rewrite: Adheres more closely to 'fast read/write' examples in TRM. up to 50x faster Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/903 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-02-06build: cleanup src/target directorySpencer Oliver1-1/+1
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2011-09-30armv7a ,cortex a : add L1, L2 cache support, va to pa supportMichel Jaouen1-0/+3
2011-01-31arm_dpm: add some SCR/RCR macrosAaron Carroll1-2/+8
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
2010-12-29Compilation Warnings on OS X 10.5Andrew MacIsaac1-2/+2
I received a number of "-Wshadow" related warnings (treated as errors) while trying to build on OS X Leopard. In addition, there were two miscellaneous other warnings in the flash drivers. Attached are two patches which correct these issues and the commit messages to accompany them. My system has the following configuration (taken from uname -a): Darwin 9.8.0 Darwin Kernel Version 9.8.0: Wed Jul 15 16:55:01 PDT 2009; root:xnu-1228.15.4~1/RELEASE_I386 i386 === Werror_patch.txt Commit Message === compilation: fixes for -Wshadow warnings on OS X These changes fix -Wshadow compilation warnings on OS X 10.5.8 Compiled with the following configure command: ../configure --prefix=/usr/local --enable-maintainer-mode --enable-jlink --enable-ft2232_libftdi === flash_patch.txt Commit Message === compilation: fixes for flash driver warnings on OS X These changes fix two compilation warnings on OS X 10.5.8: ../../../../src/flash/nor/at91sam3.c:2767: warning: redundant redeclaration of 'at91sam3_flash' ../../../../src/flash/nor/at91sam3.c:101: warning: previous declaration of 'at91sam3_flash' was here and ../../../../src/flash/nor/stmsmi.c:205: warning: format not a string literal and no format arguments Compiled with the following configure command: ../configure --prefix=/usr/local --enable-maintainer-mode --enable-jlink --enable-ft2232_libftdi === Andrew
2009-12-11ARM DPM: support updating HW breakpointsDavid Brownell1-11/+9
Abstract the DPM breakpoint and watchpoint data structures to have a shared core for housekeeping. Abstract the code updating the watchpoint registers so that it can be used to update breakpoint registers. Then do so, when something has set up the breakpoint state used by this code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03ARM DPM: share debug reason logicDavid Brownell1-0/+5
No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03ARM11: use shared DSCR bit namesDavid Brownell1-0/+1
For the bits now defined in "arm_dpm.h", switch to the shared DSCR_* symbol and remove the ARM11_DSCR_* version. Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_* sibling symbol. (Note: for both ARM11 and Cortex-A8, this should arguably be enabled by default when single stepping.) Remove some other unused declarations in "arm11.h". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03ARM DPM: make DSCR bit defs sharableDavid Brownell1-0/+14
Move the symbols for these bits from "armv7a.h" to "arm_dpm.h", where they can be seen and used not just by Cortex-A but also by the ARM11 (armv6) code. Change them from bit numbers to bit masks ... this matches the usage in ARM11 code, and also makes it easier to read. Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's enabling ITR functionality, not external interrupts, so this changes the name to be less misleading. (There *IS* a bit affecting interrupts, and this isn't it.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-02ARM DPM: tweak initializationDavid Brownell1-1/+1
Move the initial breakpoint/watchpoint disable calls to arm_dpm_initialize(), and start using that routine. This split helps with arm11 support.
2009-12-02ARMv7a/Cortex-A8: report watchpoint trigger insnDavid Brownell1-0/+5
Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-01ARM: core DPM support for watchpointsDavid Brownell1-4/+48
This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-24Cortex-A8: implement DPMDavid Brownell1-0/+3
This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-24ARM: new DPM interfaceDavid Brownell1-0/+87
First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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