diff options
| author | Evan Hunter <ehunter@broadcom.com> | 2012-10-23 15:48:41 +1100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-03-15 15:50:42 +0000 |
| commit | 927e53f8d5e6ebaf52be82cb7300cbbb471a92bb (patch) | |
| tree | 11bbaffaeb2088d450135eb52515b94da17f795a /src/target/arm_dpm.h | |
| parent | 700e7605fe63571f6b912ce994c2f1eb1fd4fe92 (diff) | |
| download | riscv-openocd-927e53f8d5e6ebaf52be82cb7300cbbb471a92bb.zip riscv-openocd-927e53f8d5e6ebaf52be82cb7300cbbb471a92bb.tar.gz riscv-openocd-927e53f8d5e6ebaf52be82cb7300cbbb471a92bb.tar.bz2 | |
cortex_a : optimize apb read/write access.
Rewrite: Adheres more closely to 'fast read/write' examples in TRM.
up to 50x faster
Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/903
Tested-by: jenkins
Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/arm_dpm.h')
| -rw-r--r-- | src/target/arm_dpm.h | 63 |
1 files changed, 50 insertions, 13 deletions
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index 66b2b1d..8d2638e 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -140,21 +140,58 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp); void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar); -/* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1. +/* DSCR bits; see ARMv7a arch spec section C10.3.1. * Not all v7 bits are valid in v6. */ -#define DSCR_CORE_HALTED (1 << 0) -#define DSCR_CORE_RESTARTED (1 << 1) -#define DSCR_INT_DIS (1 << 11) -#define DSCR_ITR_EN (1 << 13) -#define DSCR_HALT_DBG_MODE (1 << 14) -#define DSCR_MON_DBG_MODE (1 << 15) -#define DSCR_INSTR_COMP (1 << 24) -#define DSCR_DTR_TX_FULL (1 << 29) -#define DSCR_DTR_RX_FULL (1 << 30) - -#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf) -#define DSCR_RUN_MODE(dscr) ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) +#define DSCR_CORE_HALTED (0x1 << 0) +#define DSCR_CORE_RESTARTED (0x1 << 1) +#define DSCR_ENTRY_MASK (0xF << 2) +#define DSCR_STICKY_ABORT_PRECISE (0x1 << 6) +#define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7) +#define DSCR_STICKY_UNDEFINED (0x1 << 8) +#define DSCR_DBG_NOPWRDWN (0x1 << 9) /* v6 only */ +#define DSCR_DBG_ACK (0x1 << 10) +#define DSCR_INT_DIS (0x1 << 11) +#define DSCR_CP14_USR_COMMS (0x1 << 12) +#define DSCR_ITR_EN (0x1 << 13) +#define DSCR_HALT_DBG_MODE (0x1 << 14) +#define DSCR_MON_DBG_MODE (0x1 << 15) +#define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16) +#define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17) +#define DSCR_NON_SECURE (0x1 << 18) +#define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19) +#define DSCR_EXT_DCC_MASK (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */ +#define DSCR_INSTR_COMP (0x1 << 24) +#define DSCR_PIPE_ADVANCE (0x1 << 25) +#define DSCR_DTRTX_FULL_LATCHED (0x1 << 26) +#define DSCR_DTRRX_FULL_LATCHED (0x1 << 27) /* bit 28 is reserved */ +#define DSCR_DTR_TX_FULL (0x1 << 29) +#define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */ + +#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf) +#define DSCR_RUN_MODE(dscr) ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) + + +/* Methods of entry into debug mode */ +#define DSCR_ENTRY_HALT_REQ (0x0 << 2) +#define DSCR_ENTRY_BREAKPOINT (0x1 << 2) +#define DSCR_ENTRY_IMPRECISE_WATCHPT (0x2 << 2) +#define DSCR_ENTRY_BKPT_INSTR (0x3 << 2) +#define DSCR_ENTRY_EXT_DBG_REQ (0x4 << 2) +#define DSCR_ENTRY_VECT_CATCH (0x5 << 2) +#define DSCR_ENTRY_D_SIDE_ABORT (0x6 << 2) /* v6 only */ +#define DSCR_ENTRY_I_SIDE_ABORT (0x7 << 2) /* v6 only */ +#define DSCR_ENTRY_OS_UNLOCK (0x8 << 2) +#define DSCR_ENTRY_PRECISE_WATCHPT (0xA << 2) + +/* DTR modes */ +#define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20) +#define DSCR_EXT_DCC_STALL_MODE (0x1 << 20) +#define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */ + + + + /* DRCR (debug run control register) bits */ #define DRCR_HALT (1 << 0) |