diff options
| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-09-16 11:34:03 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-10 14:01:38 +0100 |
| commit | d8abda4bd828f40fc76613f4d809d86f4c6f1c97 (patch) | |
| tree | a78a2ffaf2a9d2039c4447f96252e758d9fed45e /src/target/arm_dpm.h | |
| parent | 391109505fff97772c70f7dda02865e7a9863007 (diff) | |
| download | riscv-openocd-d8abda4bd828f40fc76613f4d809d86f4c6f1c97.zip riscv-openocd-d8abda4bd828f40fc76613f4d809d86f4c6f1c97.tar.gz riscv-openocd-d8abda4bd828f40fc76613f4d809d86f4c6f1c97.tar.bz2 | |
aarch64: fix entry into debug state
- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this
bit are ignored but we should not do them anyway
- use dpmv8 function to report the reason for debug entry
- WFAR is a 64bit register
Change-Id: I07b81ecf105ceb7c3ae2f764bb408eb973c1d1de
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Diffstat (limited to 'src/target/arm_dpm.h')
| -rw-r--r-- | src/target/arm_dpm.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index ad49b8c..27badf4 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -138,7 +138,7 @@ struct arm_dpm { struct dpm_wp *dwp; /** Address of the instruction which triggered a watchpoint. */ - uint32_t wp_pc; + target_addr_t wp_pc; /** Recent value of DSCR. */ uint32_t dscr; |