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authorAntonio Borneo <borneo.antonio@gmail.com>2020-04-26 01:07:27 +0200
committerAntonio Borneo <borneo.antonio@gmail.com>2020-05-09 14:38:40 +0100
commit5df5e89cf3caf02dc6f49a5d3c8aa8b1349a1dbf (patch)
tree14d9a553fd1d2d27c15f1b208569c5364e231493 /tcl/board/phytec_lpc3250.cfg
parent6d3cb807aaa60c4a4cd8ed49ae7860097bc1b3ce (diff)
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tcl: remove trailing whitespace
The script checkpatch available in new Linux kernel offers an experimental feature for automatically fix the code in place. While still experimental, the feature works quite well for simple fixes, like spacing. This patch has been created automatically with the script under review for inclusion in OpenOCD, using the command: find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types TRAILING_WHITESPACE --fix-inplace -f {} \; The patch only changes amount and position of whitespace, thus the following commands show empty diff git diff -w git log -w -p git log -w --stat Change-Id: Ie7e3a236f4db9c70019e3b3c7e851edbd3a9dd84 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5616 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
Diffstat (limited to 'tcl/board/phytec_lpc3250.cfg')
-rw-r--r--tcl/board/phytec_lpc3250.cfg10
1 files changed, 5 insertions, 5 deletions
diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index 1c48f5d..cee28cd 100644
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -23,12 +23,12 @@ $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
# Bare-bones initialization of core clocks and SDRAM
proc phytec_lpc3250_init { } {
- # Set clock dividers
+ # Set clock dividers
# ARMCLK = 266.5 MHz
# HCLK = 133.25 MHz
# PERIPHCLK = 13.325 MHz
mww 0x400040BC 0
- mww 0x40004050 0x140
+ mww 0x40004050 0x140
mww 0x40004040 0x4D
mww 0x40004058 0x16250
@@ -37,7 +37,7 @@ proc phytec_lpc3250_init { } {
sleep 1 busy
mww 0x40004044 0x106
sleep 1 busy
- mww 0x40004044 0x006
+ mww 0x40004044 0x006
sleep 1 busy
mww 0x40004048 0x2
@@ -49,7 +49,7 @@ proc phytec_lpc3250_init { } {
mww 0x31080008 0
mww 0x40004068 0x1C000
mww 0x31080028 0x11
-
+
mww 0x31080400 0
mww 0x31080440 0
mww 0x31080460 0
@@ -66,7 +66,7 @@ proc phytec_lpc3250_init { } {
mww 0x31080054 1
mww 0x31080058 1
mww 0x3108005C 0
-
+
mww 0x31080100 0x5680
mww 0x31080104 0x302