Age | Commit message (Collapse) | Author | Files | Lines | |
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2024-05-05 | Add unratified Ssdbltrp and Smdbltrp fields (#238) | Ved Shanbhogue | 1 | -7/+18 | |
* Add Ssdbltrp, Smdbltrp, and Sddbltrp fields * Add Ssdbltrp, Smdbltrp, and Sddbltrp fields * renasme pcerr to cetrig; fix fields of dcsr to match 1.0 spec | |||||
2024-05-05 | Mark Zihintntl, Zicond, Zfa, Zbkb, and Zvbc as ratified (#246) | Ved Shanbhogue | 24 | -29/+22 | |
* Mark Zihintntl as ratified * Mark Zicond as ratified * Mark Zfa as ratified * Mark Zvbc as ratified * Mark Zbkb ratified * Mark xperm4/8 of Zbkx as ratified * Update Zbkb - remove Zbe | |||||
2024-05-05 | Mark Zimop and Zcmop ratified (#245) | Ved Shanbhogue | 2 | -0/+0 | |
2024-05-05 | Mark Zabha ratified (#244) | Ved Shanbhogue | 1 | -0/+0 | |
2024-05-01 | Remove remainder of B extensions | Andrew Waterman | 2 | -21/+0 | |
Continuation of f0c6e9575f640e31a591b03f6bced408e9e08bac | |||||
2024-05-01 | Remove remainder of P extensions | Andrew Waterman | 2 | -39/+0 | |
Continuation of e07ce62356e1f9a4497ec004fda5e6d5aadfcd48 | |||||
2024-05-01 | Add shadow stack fault code | Andrew Waterman | 1 | -0/+1 | |
2024-05-01 | Remove legacy bit-manipulation extensions | Andrew Waterman | 12 | -65/+0 | |
These do not have a path to ratification. I left the ones that are generic versions of ratified instructions (e.g. orc.b is a special case of gorci). | |||||
2024-05-01 | Remove old P extensions | Andrew Waterman | 6 | -293/+0 | |
See https://github.com/riscv-software-src/riscv-isa-sim/pull/1660 for explanation | |||||
2024-05-01 | Remove unratified vector memory-access instructions | Andrew Waterman | 1 | -36/+0 | |
ELEN > 64 was not actually defined and ratified. These were just hypothetical encodings. | |||||
2024-05-01 | Correctly detect overlapping encodings | Andrew Waterman | 2 | -11/+48 | |
A regression introduced a few years ago prevented detecting partially overlapping encodings; instead, we only detected exact matches. Now, we detect the partial cases. We now need to maintain two allowlists (overlapping_extensions and overlapping_instructions) for the cases that extensions and/or instructions overlap by design. | |||||
2024-05-01 | Remove RV128 for now | Andrew Waterman | 4 | -44/+1 | |
It is highly speculative at this point, but it adds maintenance burden. | |||||
2024-05-01 | Remove legacy bitmanip encodings that are now conflicting | Andrew Waterman | 2 | -8/+0 | |
Zbt (cmov) conflicts with ratified Zicond (czero.eqz) Zbm will conflict with soon-to-be-frozen Zpa | |||||
2024-04-10 | Add mstateen0[60] for Smcsrind/Sscsrind (#241) | YenHaoChen | 1 | -0/+4 | |
Signed-off-by: Andrew Waterman <andrew@sifive.com> Co-authored-by: Andrew Waterman <andrew@sifive.com> | |||||
2024-04-10 | Add stateen0[59] for AIA (#242) | YenHaoChen | 1 | -0/+4 | |
2024-03-01 | move opcode of zvb* (#236) | Lucas | 9 | -0/+0 | |
* move opcode of zvbb * move all zvk* out | |||||
2024-02-26 | Add definition of low-priority and high-priority RAS event from AIA (#234) | YenHaoChen | 1 | -15/+19 | |
2024-02-21 | Merge pull request #232 from YenHaoChen/pr-mtopi | Neel Gala | 1 | -0/+3 | |
Add CSR fields of mtopi | |||||
2024-02-21 | Add CSR fields of mtopi | YenHaoChen | 1 | -0/+3 | |
2024-02-18 | Remove erroneous MSTATEEN0[H]_HENVCFGH macros (#230) | Andrew Waterman | 1 | -2/+0 | |
MSTATEEN0[H]_HENVCFG should be used instead. Resolves #229 | |||||
2024-02-15 | Add CSR fields of hvictl (#228) | YenHaoChen | 1 | -0/+6 | |
2024-02-12 | Made Typo correction in READ.MD (#223) (#227) | akshaykumars614 | 1 | -1/+1 | |
2024-02-03 | Add Zicfilp codes (#225) | mylai-mtk | 3 | -0/+6 | |
2024-01-08 | Add `.rv32` on rv32_zbs and rv32_zbb instructions (#220) | hirooih | 7 | -15/+22 | |
* Add .rv32 on rv32_zbs instructions to be consistent with slli, srli, and srai. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> * Add .rv32 on rv32_zbb instructions - zext.h.rv32, rev8.rv32, and rori.rev32 - rev8.rv32, and rori.rev32 are also aliased in rv32_{zk,zkn,zks,zbkb} - only rv32_zks is shown in the extension field Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> --------- Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> | |||||
2024-01-08 | Add missing `-n0` (#219) | hirooih | 2 | -4/+4 | |
add `_n0' on `rd` for `c.li`, `c.mv`, `c.add`, and `c.lqsp`. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> | |||||
2023-12-25 | update mstateen0 fields (#218) | Ved Shanbhogue | 1 | -1/+4 | |
2023-12-23 | Merge pull request #216 from ved-rivos/ssqosid | Andrew Waterman | 2 | -0/+5 | |
Add unratified srmcfg CSR | |||||
2023-12-23 | Merge pull request #217 from ved-rivos/zacas_ratified | Andrew Waterman | 2 | -0/+0 | |
Update Zacas as ratified | |||||
2023-12-23 | mark zacas ratified | Ved Shanbhogue | 2 | -0/+0 | |
2023-12-23 | add srmcfg CSR | Ved Shanbhogue | 2 | -0/+5 | |
2023-11-27 | Merge pull request #212 from ved-rivos/sw_check_exception | Andrew Waterman | 1 | -0/+2 | |
Add software check and hardware error faults | |||||
2023-11-27 | Merge pull request #211 from ved-rivos/zicfiss_insts | Andrew Waterman | 3 | -0/+26 | |
Add unratified Zicfiss extension instructions | |||||
2023-11-27 | CSR fields introduced by Zicfilp (#210) | Ved Shanbhogue | 1 | -0/+8 | |
2023-11-25 | add software check and hardware error faults | Ved Shanbhogue | 1 | -0/+2 | |
2023-11-25 | add zicfiss instructions | Ved Shanbhogue | 1 | -0/+14 | |
2023-11-25 | add compressed zicfiss instructions | Ved Shanbhogue | 1 | -0/+5 | |
2023-11-25 | add pseudoops for zicfiss insts | Ved Shanbhogue | 1 | -0/+7 | |
2023-11-24 | Merge pull request #209 from ved-rivos/zicfiss | Andrew Waterman | 2 | -0/+4 | |
Add CSR fields and SSP CSR introduced by unratified Zicfiss extension | |||||
2023-11-24 | SSP CSR introduced by Zicfiss | Ved Shanbhogue | 1 | -0/+1 | |
2023-11-24 | CSR fields introduced by Zicfiss | Ved Shanbhogue | 1 | -0/+3 | |
2023-11-01 | Merge pull request #206 from ved-rivos/zabha | Andrew Waterman | 1 | -0/+23 | |
Add unratified Zabha extension | |||||
2023-10-29 | Add Zabha AMO inst code points | Ved Shanbhogue | 1 | -0/+23 | |
2023-10-26 | Merge pull request #205 from tomhepworth/master | Andrew Waterman | 1 | -1/+3 | |
Clarified syntax of regular instructions | |||||
2023-10-26 | Clarified syntax of regular instructions | Thomas Hepworth | 1 | -1/+3 | |
See https://github.com/riscv/riscv-opcodes/issues/204 Before this change the text implied that bit encodings and variable arguments could not be mixed in the list of instruction arguments. Signed-off-by: Thomas Hepworth <tomhepworth@hotmail.co.uk> | |||||
2023-10-20 | Merge pull request #201 from mehnadnerd/master | Andrew Waterman | 1 | -0/+8 | |
Adding Zalasr | |||||
2023-10-19 | Making explicit that the aq bit is set for load-acquire, rl bit is set for ↵ | brs | 1 | -8/+8 | |
store-releasee | |||||
2023-10-18 | Changing it so Zalasr has one bit hardcoded for each, to reduce opcode ↵ | brs | 1 | -8/+8 | |
confusion hopefully | |||||
2023-10-18 | Adding load-acquire/store-release. Note they are written here as `lb.` for ↵ | brs | 1 | -0/+8 | |
the load-acquire byte (so `lb.aq` and `lb.aqrl`), I'm not sure that will work but it passes the tests here. | |||||
2023-10-17 | Add pseudo-instructions for Zimop/Zcmop (#194) | Ved Shanbhogue | 3 | -51/+114 | |
* add mop.r.N and mop.rr.N pseudo-inst * add c.mop.N pseudo-inst * add arg_lut entries and emitted pseudoops for Zimop/Zcmop * add pseudoinsts for Zimop * add pseudoinsts for Zcmop * update zcmop mnemonics * update zcmop mnemonics | |||||
2023-10-17 | Merge pull request #202 from a4lg/remove-zvamo | Andrew Waterman | 1 | -41/+0 | |
Remove unratified `Zvamo` instructions from `rv_v` |